Commit 9aec7222 authored by Taimur Hassan's avatar Taimur Hassan Committed by Alex Deucher
Browse files

drm/amd/display: [FW Promotion] Release 0.0.246.0 



Reviewed-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarTaimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a1fc2837

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

+103 −51
Original line number Diff line number Diff line
@@ -475,11 +475,23 @@ union replay_hw_flags { 
		 * Use TPS3 signal when restore main link.

		 */

		uint32_t force_wakeup_by_tps3 : 1;

		/**

		 * @is_alpm_initialized: Indicates whether ALPM is initialized

		 */

		uint32_t is_alpm_initialized : 1;

	} bitfields;



	uint32_t u32All;

};



union fw_assisted_mclk_switch_version {

	struct {

		uint8_t minor : 5;

		uint8_t major : 3;

	};

	uint8_t ver;

};



/**

 * DMUB feature capabilities.

 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
@@ -1823,52 +1835,11 @@ enum fams2_stream_type { 
	FAMS2_STREAM_TYPE_SUBVP = 4,

};



/* dynamic stream state */

struct dmub_fams2_legacy_stream_dynamic_state {

	uint8_t force_allow_at_vblank;

	uint8_t pad[3];

};



struct dmub_fams2_subvp_stream_dynamic_state {

	uint16_t viewport_start_hubp_vline;

	uint16_t viewport_height_hubp_vlines;

	uint16_t viewport_start_c_hubp_vline;

	uint16_t viewport_height_c_hubp_vlines;

	uint16_t phantom_viewport_height_hubp_vlines;

	uint16_t phantom_viewport_height_c_hubp_vlines;

	uint16_t microschedule_start_otg_vline;

	uint16_t mall_start_otg_vline;

	uint16_t mall_start_hubp_vline;

	uint16_t mall_start_c_hubp_vline;

	uint8_t force_allow_at_vblank_only;

	uint8_t pad[3];

};



struct dmub_fams2_drr_stream_dynamic_state {

	uint16_t stretched_vtotal;

	uint8_t use_cur_vtotal;

	uint8_t pad;

};



struct dmub_fams2_stream_dynamic_state {

	uint64_t ref_tick;

	uint32_t cur_vtotal;

	uint16_t adjusted_allow_end_otg_vline;

	uint8_t pad[2];

	struct dmub_optc_position ref_otg_pos;

	struct dmub_optc_position target_otg_pos;

	union {

		struct dmub_fams2_legacy_stream_dynamic_state legacy;

		struct dmub_fams2_subvp_stream_dynamic_state subvp;

		struct dmub_fams2_drr_stream_dynamic_state drr;

	} sub_state;

};



/* static stream state */

struct dmub_fams2_legacy_stream_static_state {

	uint8_t vactive_det_fill_delay_otg_vlines;

	uint8_t programming_delay_otg_vlines;

};

}; //v0



struct dmub_fams2_subvp_stream_static_state {

	uint16_t vratio_numerator;
@@ -1887,14 +1858,59 @@ struct dmub_fams2_subvp_stream_static_state { 
	uint8_t phantom_otg_inst;

	uint8_t phantom_pipe_mask;

	uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough)

};

}; //v0



struct dmub_fams2_drr_stream_static_state {

	uint16_t nom_stretched_vtotal;

	uint8_t programming_delay_otg_vlines;

	uint8_t only_stretch_if_required;

	uint8_t pad[2];

};

}; //v0



struct dmub_fams2_cmd_legacy_stream_static_state {

	uint16_t vactive_det_fill_delay_otg_vlines;

	uint16_t programming_delay_otg_vlines;

}; //v1



struct dmub_fams2_cmd_subvp_stream_static_state {

	uint16_t vratio_numerator;

	uint16_t vratio_denominator;

	uint16_t phantom_vtotal;

	uint16_t phantom_vactive;

	uint16_t programming_delay_otg_vlines;

	uint16_t prefetch_to_mall_otg_vlines;

	union {

		struct {

			uint8_t is_multi_planar : 1;

			uint8_t is_yuv420 : 1;

		} bits;

		uint8_t all;

	} config;

	uint8_t phantom_otg_inst;

	uint8_t phantom_pipe_mask;

	uint8_t pad0;

	uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough)

	uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)];

}; //v1



struct dmub_fams2_cmd_drr_stream_static_state {

	uint16_t nom_stretched_vtotal;

	uint16_t programming_delay_otg_vlines;

	uint8_t only_stretch_if_required;

	uint8_t pad[3];

}; //v1



union dmub_fams2_stream_static_sub_state {

	struct dmub_fams2_legacy_stream_static_state legacy;

	struct dmub_fams2_subvp_stream_static_state subvp;

	struct dmub_fams2_drr_stream_static_state drr;

}; //v0



union dmub_fams2_cmd_stream_static_sub_state {

	struct dmub_fams2_cmd_legacy_stream_static_state legacy;

	struct dmub_fams2_cmd_subvp_stream_static_state subvp;

	struct dmub_fams2_cmd_drr_stream_static_state drr;

}; //v1



struct dmub_fams2_stream_static_state {

	enum fams2_stream_type type;
@@ -1924,13 +1940,45 @@ struct dmub_fams2_stream_static_state { 
	uint8_t pipe_mask; // pipe mask for the whole config

	uint8_t num_planes;

	uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough)

	uint8_t pad[DMUB_MAX_PLANES % 4];

	uint8_t pad[4 - (DMUB_MAX_PLANES % 4)];

	union dmub_fams2_stream_static_sub_state sub_state;

}; //v0



struct dmub_fams2_cmd_stream_static_base_state {

	enum fams2_stream_type type;

	uint32_t otg_vline_time_ns;

	uint32_t otg_vline_time_ticks;

	uint16_t htotal;

	uint16_t vtotal; // nominal vtotal

	uint16_t vblank_start;

	uint16_t vblank_end;

	uint16_t max_vtotal;

	uint16_t allow_start_otg_vline;

	uint16_t allow_end_otg_vline;

	uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed

	uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start

	uint16_t contention_delay_otg_vlines; // time to budget for contention on execution

	uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing

	uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline

	union {

		struct dmub_fams2_legacy_stream_static_state legacy;

		struct dmub_fams2_subvp_stream_static_state subvp;

		struct dmub_fams2_drr_stream_static_state drr;

	} sub_state;

};

		struct {

			uint8_t is_drr : 1; // stream is DRR enabled

			uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal

			uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank

		} bits;

		uint8_t all;

	} config;

	uint8_t otg_inst;

	uint8_t pipe_mask; // pipe mask for the whole config

	uint8_t num_planes;

	uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough)

	uint8_t pad[4 - (DMUB_MAX_PLANES % 4)];

}; //v1



struct dmub_fams2_stream_static_state_v1 {

	struct dmub_fams2_cmd_stream_static_base_state base;

	union dmub_fams2_cmd_stream_static_sub_state sub_state;

}; //v1



/**

 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive
@@ -1970,7 +2018,11 @@ struct dmub_cmd_fams2_global_config { 


union dmub_cmd_fams2_config {

	struct dmub_cmd_fams2_global_config global;

	struct dmub_fams2_stream_static_state stream;

	struct dmub_fams2_stream_static_state stream; //v0

	union {

		struct dmub_fams2_cmd_stream_static_base_state base;

		union dmub_fams2_cmd_stream_static_sub_state sub_state;

	} stream_v1; //v1

};



/**