Commit 9af09dfc authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/color: move pre-SKL gamma and CSC enable read to intel_color 



Abstract the register access better. The DSPCNTR read could be moved to
either i9xx_plane.c or intel_color.c. The latter feels better, even if
the register is written in the former.

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarJouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/33830dba5d69027469d976f6909740ccff8c7281.1692287501.git.jani.nikula@intel.com
parent f56e23ed

drivers/gpu/drm/i915/display/intel_color.c

+25 −0
Original line number Diff line number Diff line
@@ -1032,12 +1032,31 @@ static u32 ilk_read_csc_mode(struct intel_crtc *crtc) 
	return intel_de_read(i915, PIPE_CSC_MODE(crtc->pipe));

}



static void i9xx_get_config(struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct intel_plane *plane = to_intel_plane(crtc->base.primary);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;

	u32 tmp;



	tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));



	if (tmp & DISP_PIPE_GAMMA_ENABLE)

		crtc_state->gamma_enable = true;



	if (!HAS_GMCH(dev_priv) && tmp & DISP_PIPE_CSC_ENABLE)

		crtc_state->csc_enable = true;

}



static void hsw_get_config(struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);



	crtc_state->gamma_mode = hsw_read_gamma_mode(crtc);

	crtc_state->csc_mode = ilk_read_csc_mode(crtc);



	i9xx_get_config(crtc_state);

}



static void skl_get_config(struct intel_crtc_state *crtc_state)
@@ -3258,6 +3277,8 @@ static void chv_get_config(struct intel_crtc_state *crtc_state) 
	struct drm_i915_private *i915 = to_i915(crtc->base.dev);



	crtc_state->cgm_mode = intel_de_read(i915, CGM_PIPE_MODE(crtc->pipe));



	i9xx_get_config(crtc_state);

}



static void chv_read_luts(struct intel_crtc_state *crtc_state)
@@ -3328,6 +3349,8 @@ static void ilk_get_config(struct intel_crtc_state *crtc_state) 
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);



	crtc_state->csc_mode = ilk_read_csc_mode(crtc);



	i9xx_get_config(crtc_state);

}



static void ilk_read_luts(struct intel_crtc_state *crtc_state)
@@ -3654,6 +3677,7 @@ static const struct intel_color_funcs i965_color_funcs = { 
	.load_luts = i965_load_luts,

	.read_luts = i965_read_luts,

	.lut_equal = i965_lut_equal,

	.get_config = i9xx_get_config,

};



static const struct intel_color_funcs i9xx_color_funcs = {
@@ -3662,6 +3686,7 @@ static const struct intel_color_funcs i9xx_color_funcs = { 
	.load_luts = i9xx_load_luts,

	.read_luts = i9xx_read_luts,

	.lut_equal = i9xx_lut_equal,

	.get_config = i9xx_get_config,

};



static const struct intel_color_funcs tgl_color_funcs = {

drivers/gpu/drm/i915/display/intel_display.c

+0 −23
Original line number Diff line number Diff line
@@ -2869,24 +2869,6 @@ bdw_get_pipe_misc_output_format(struct intel_crtc *crtc) 
	}

}



static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct intel_plane *plane = to_intel_plane(crtc->base.primary);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;

	u32 tmp;



	tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));



	if (tmp & DISP_PIPE_GAMMA_ENABLE)

		crtc_state->gamma_enable = true;



	if (!HAS_GMCH(dev_priv) &&

	    tmp & DISP_PIPE_CSC_ENABLE)

		crtc_state->csc_enable = true;

}



static bool i9xx_get_pipe_config(struct intel_crtc *crtc,

				 struct intel_crtc_state *pipe_config)

{
@@ -2942,7 +2924,6 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 
	    (tmp & TRANSCONF_WGC_ENABLE))

		pipe_config->wgc_enable = true;



	i9xx_get_pipe_color_config(pipe_config);

	intel_color_get_config(pipe_config);



	if (DISPLAY_VER(dev_priv) < 4)
@@ -3340,7 +3321,6 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc, 


	pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);



	i9xx_get_pipe_color_config(pipe_config);

	intel_color_get_config(pipe_config);



	pipe_config->pixel_multiplier = 1;
@@ -3731,9 +3711,6 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, 


	pipe_config->sink_format = pipe_config->output_format;



	if (DISPLAY_VER(dev_priv) < 9)

		i9xx_get_pipe_color_config(pipe_config);



	intel_color_get_config(pipe_config);



	tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));