Commit 9afaa16c authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2025-04-09' of... 

Merge tag 'drm-intel-fixes-2025-04-09' of https://gitlab.freedesktop.org/drm/i915/kernel

 into drm-fixes

drm/i915 fixes for v6.15-rc2:
- Fix scanline offset for LNL+ and BMG+
- Fix GVT unterminated-string-initialization build warning
- Fix DP rate limit when sink doesn't support TPS4
- Handle GDDR + ECC memory type detection
- Fix VRR parameter change check
- Fix fence not released on early probe errors
- Disable render power gating during live selftests

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://lore.kernel.org/r/87lds9wlpq.fsf@intel.com
parents 0af2f6be e3ea2eae

drivers/gpu/drm/i915/display/intel_bw.c

+13 −1
Original line number Diff line number Diff line
@@ -244,6 +244,7 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv, 
			qi->deinterleave = 4;

			break;

		case INTEL_DRAM_GDDR:

		case INTEL_DRAM_GDDR_ECC:

			qi->channel_width = 32;

			break;

		default:
@@ -398,6 +399,12 @@ static const struct intel_sa_info xe2_hpd_sa_info = { 
	/* Other values not used by simplified algorithm */

};



static const struct intel_sa_info xe2_hpd_ecc_sa_info = {

	.derating = 45,

	.deprogbwlimit = 53,

	/* Other values not used by simplified algorithm */

};



static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)

{

	struct intel_qgv_info qi = {};
@@ -740,10 +747,15 @@ static unsigned int icl_qgv_bw(struct drm_i915_private *i915, 


void intel_bw_init_hw(struct drm_i915_private *dev_priv)

{

	const struct dram_info *dram_info = &dev_priv->dram_info;



	if (!HAS_DISPLAY(dev_priv))

		return;



	if (DISPLAY_VERx100(dev_priv) >= 1401 && IS_DGFX(dev_priv))

	if (DISPLAY_VERx100(dev_priv) >= 1401 && IS_DGFX(dev_priv) &&

		 dram_info->type == INTEL_DRAM_GDDR_ECC)

		xe2_hpd_get_bw_info(dev_priv, &xe2_hpd_ecc_sa_info);

	else if (DISPLAY_VERx100(dev_priv) >= 1401 && IS_DGFX(dev_priv))

		xe2_hpd_get_bw_info(dev_priv, &xe2_hpd_sa_info);

	else if (DISPLAY_VER(dev_priv) >= 14)

		tgl_get_bw_info(dev_priv, &mtl_sa_info);

drivers/gpu/drm/i915/display/intel_display.c

+3 −1
Original line number Diff line number Diff line
@@ -968,7 +968,9 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state, 
		old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin ||

		old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax ||

		old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband ||

		old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;

		old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full ||

		old_crtc_state->vrr.vsync_start != new_crtc_state->vrr.vsync_start ||

		old_crtc_state->vrr.vsync_end != new_crtc_state->vrr.vsync_end;

}



static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

+42 −7
Original line number Diff line number Diff line
@@ -172,10 +172,28 @@ int intel_dp_link_symbol_clock(int rate) 


static int max_dprx_rate(struct intel_dp *intel_dp)

{

	struct intel_display *display = to_intel_display(intel_dp);

	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

	int max_rate;



	if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))

		return drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);

		max_rate = drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);

	else

		max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);



	/*

	 * Some broken eDP sinks illegally declare support for

	 * HBR3 without TPS4, and are unable to produce a stable

	 * output. Reject HBR3 when TPS4 is not available.

	 */

	if (max_rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd)) {

		drm_dbg_kms(display->drm,

			    "[ENCODER:%d:%s] Rejecting HBR3 due to missing TPS4 support\n",

			    encoder->base.base.id, encoder->base.name);

		max_rate = 540000;

	}



	return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);

	return max_rate;

}



static int max_dprx_lane_count(struct intel_dp *intel_dp)
@@ -4170,6 +4188,9 @@ static void intel_edp_mso_init(struct intel_dp *intel_dp) 
static void

intel_edp_set_sink_rates(struct intel_dp *intel_dp)

{

	struct intel_display *display = to_intel_display(intel_dp);

	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;



	intel_dp->num_sink_rates = 0;



	if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
@@ -4180,10 +4201,7 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp) 
				 sink_rates, sizeof(sink_rates));



		for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {

			int val = le16_to_cpu(sink_rates[i]);



			if (val == 0)

				break;

			int rate;



			/* Value read multiplied by 200kHz gives the per-lane

			 * link rate in kHz. The source rates are, however,
@@ -4191,7 +4209,24 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp) 
			 * back to symbols is

			 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)

			 */

			intel_dp->sink_rates[i] = (val * 200) / 10;

			rate = le16_to_cpu(sink_rates[i]) * 200 / 10;



			if (rate == 0)

				break;



			/*

			 * Some broken eDP sinks illegally declare support for

			 * HBR3 without TPS4, and are unable to produce a stable

			 * output. Reject HBR3 when TPS4 is not available.

			 */

			if (rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd)) {

				drm_dbg_kms(display->drm,

					    "[ENCODER:%d:%s] Rejecting HBR3 due to missing TPS4 support\n",

					    encoder->base.base.id, encoder->base.name);

				break;

			}



			intel_dp->sink_rates[i] = rate;

		}

		intel_dp->num_sink_rates = i;

	}

drivers/gpu/drm/i915/display/intel_vblank.c

+3 −1
Original line number Diff line number Diff line
@@ -222,7 +222,9 @@ int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state) 
	 * However if queried just before the start of vblank we'll get an

	 * answer that's slightly in the future.

	 */

	if (DISPLAY_VER(display) == 2)

	if (DISPLAY_VER(display) >= 20 || display->platform.battlemage)

		return 1;

	else if (DISPLAY_VER(display) == 2)

		return -1;

	else if (HAS_DDI(display) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

		return 2;

drivers/gpu/drm/i915/gt/intel_rc6.c

+4 −15
Original line number Diff line number Diff line
@@ -117,17 +117,6 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) 
			GEN6_RC_CTL_RC6_ENABLE |

			GEN6_RC_CTL_EI_MODE(1);



	/*

	 * BSpec 52698 - Render powergating must be off.

	 * FIXME BSpec is outdated, disabling powergating for MTL is just

	 * temporary wa and should be removed after fixing real cause

	 * of forcewake timeouts.

	 */

	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)))

		pg_enable =

			GEN9_MEDIA_PG_ENABLE |

			GEN11_MEDIA_SAMPLER_PG_ENABLE;

	else

	pg_enable =

		GEN9_RENDER_PG_ENABLE |

		GEN9_MEDIA_PG_ENABLE |