Commit 9b0dddd5 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915: pass dev_priv explicitly to EDP_PSR2_CTL 



Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the EDP_PSR2_CTL register macro.

Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e7df99445716ce404bbfe733dd962288a529cf0d.1714471597.git.jani.nikula@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 83f4ccb3

drivers/gpu/drm/i915/display/intel_psr.c

+9 −6
Original line number Diff line number Diff line
@@ -932,7 +932,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) 
	 */

	intel_de_write(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder), psr_val);



	intel_de_write(dev_priv, EDP_PSR2_CTL(cpu_transcoder), val);

	intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv, cpu_transcoder), val);

}



static bool
@@ -963,7 +963,7 @@ static void psr2_program_idle_frames(struct intel_dp *intel_dp, 
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;



	intel_de_rmw(dev_priv, EDP_PSR2_CTL(cpu_transcoder),

	intel_de_rmw(dev_priv, EDP_PSR2_CTL(dev_priv, cpu_transcoder),

		     EDP_PSR2_IDLE_FRAMES_MASK,

		     EDP_PSR2_IDLE_FRAMES(idle_frames));

}
@@ -1700,7 +1700,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp) 


	drm_WARN_ON(&dev_priv->drm,

		    transcoder_has_psr2(dev_priv, cpu_transcoder) &&

		    intel_de_read(dev_priv, EDP_PSR2_CTL(cpu_transcoder)) & EDP_PSR2_ENABLE);

		    intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv, cpu_transcoder)) & EDP_PSR2_ENABLE);



	drm_WARN_ON(&dev_priv->drm,

		    intel_de_read(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder)) & EDP_PSR_ENABLE);
@@ -2011,7 +2011,8 @@ static void intel_psr_exit(struct intel_dp *intel_dp) 


	if (!intel_dp->psr.active) {

		if (transcoder_has_psr2(dev_priv, cpu_transcoder)) {

			val = intel_de_read(dev_priv, EDP_PSR2_CTL(cpu_transcoder));

			val = intel_de_read(dev_priv,

					    EDP_PSR2_CTL(dev_priv, cpu_transcoder));

			drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE);

		}
@@ -2027,7 +2028,8 @@ static void intel_psr_exit(struct intel_dp *intel_dp) 
	} else if (intel_dp->psr.psr2_enabled) {

		tgl_disallow_dc3co_on_psr2_exit(intel_dp);



		val = intel_de_rmw(dev_priv, EDP_PSR2_CTL(cpu_transcoder),

		val = intel_de_rmw(dev_priv,

				   EDP_PSR2_CTL(dev_priv, cpu_transcoder),

				   EDP_PSR2_ENABLE, 0);



		drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE));
@@ -3529,7 +3531,8 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) 
		val = intel_de_read(dev_priv, TRANS_DP2_CTL(cpu_transcoder));

		enabled = val & TRANS_DP2_PANEL_REPLAY_ENABLE;

	} else if (psr->psr2_enabled) {

		val = intel_de_read(dev_priv, EDP_PSR2_CTL(cpu_transcoder));

		val = intel_de_read(dev_priv,

				    EDP_PSR2_CTL(dev_priv, cpu_transcoder));

		enabled = val & EDP_PSR2_ENABLE;

	} else {

		val = intel_de_read(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_psr_regs.h

+1 −1
Original line number Diff line number Diff line
@@ -153,7 +153,7 @@ 


#define _PSR2_CTL_A				0x60900

#define _PSR2_CTL_EDP				0x6f900

#define EDP_PSR2_CTL(tran)			_MMIO_TRANS2(dev_priv, tran, _PSR2_CTL_A)

#define EDP_PSR2_CTL(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _PSR2_CTL_A)

#define   EDP_PSR2_ENABLE			REG_BIT(31)

#define   EDP_SU_TRACK_ENABLE			REG_BIT(30) /* up to adl-p */

#define   TGL_EDP_PSR2_BLOCK_COUNT_MASK		REG_BIT(28)