Commit 9b5fd115 authored by Pierre-Louis Bossart's avatar Pierre-Louis Bossart Committed by Vinod Koul
Browse files

soundwire: intel_ace2.x: add AC timing extensions for PantherLake 



The ACE3 IP used in PantherLake exposes new bitfields in the ACTMCTL
register to better control clocks/delays. These bitfields were
reserved/zero in the ACE2.x IP, to simplify the integration the new
bifields are added unconditionally. The behavior will only be impacted
when the firmware exposes DSD properties to set non-zero values.

Signed-off-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: default avatarPéter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: default avatarRanjani Sridharan <ranjani.sridharan@linux.intel.com>
Signed-off-by: default avatarBard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20240603070240.5165-1-yung-chuan.liao@linux.intel.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent a5b7365f

drivers/soundwire/intel.h

+5 −0
Original line number Diff line number Diff line
@@ -59,6 +59,11 @@ struct sdw_intel { 
};



struct sdw_intel_prop {

	u16 clde;

	u16 doaise2;

	u16 dodse2;

	u16 clds;

	u16 clss;

	u16 doaise;

	u16 doais;

	u16 dodse;

drivers/soundwire/intel_ace2x.c

+15 −0
Original line number Diff line number Diff line
@@ -27,6 +27,11 @@ static void intel_shim_vs_init(struct sdw_intel *sdw) 
	void __iomem *shim_vs = sdw->link_res->shim_vs;

	struct sdw_bus *bus = &sdw->cdns.bus;

	struct sdw_intel_prop *intel_prop;

	u16 clde;

	u16 doaise2;

	u16 dodse2;

	u16 clds;

	u16 clss;

	u16 doaise;

	u16 doais;

	u16 dodse;
@@ -34,12 +39,22 @@ static void intel_shim_vs_init(struct sdw_intel *sdw) 
	u16 act;



	intel_prop = bus->vendor_specific_prop;

	clde = intel_prop->clde;

	doaise2 = intel_prop->doaise2;

	dodse2 = intel_prop->dodse2;

	clds = intel_prop->clds;

	clss = intel_prop->clss;

	doaise = intel_prop->doaise;

	doais = intel_prop->doais;

	dodse = intel_prop->dodse;

	dods = intel_prop->dods;



	act = intel_readw(shim_vs, SDW_SHIM2_INTEL_VS_ACTMCTL);

	u16p_replace_bits(&act, clde, SDW_SHIM3_INTEL_VS_ACTMCTL_CLDE);

	u16p_replace_bits(&act, doaise2, SDW_SHIM3_INTEL_VS_ACTMCTL_DOAISE2);

	u16p_replace_bits(&act, dodse2, SDW_SHIM3_INTEL_VS_ACTMCTL_DODSE2);

	u16p_replace_bits(&act, clds, SDW_SHIM3_INTEL_VS_ACTMCTL_CLDS);

	u16p_replace_bits(&act, clss, SDW_SHIM3_INTEL_VS_ACTMCTL_CLSS);

	u16p_replace_bits(&act, doaise, SDW_SHIM2_INTEL_VS_ACTMCTL_DOAISE);

	u16p_replace_bits(&act, doais, SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS);

	u16p_replace_bits(&act, dodse, SDW_SHIM2_INTEL_VS_ACTMCTL_DODSE);

drivers/soundwire/intel_auxdevice.c

+20 −0
Original line number Diff line number Diff line
@@ -159,11 +159,31 @@ static int sdw_master_read_intel_prop(struct sdw_bus *bus) 
		return -ENOMEM;



	/* initialize with hardware defaults, in case the properties are not found */

	intel_prop->clde = 0x0;

	intel_prop->doaise2 = 0x0;

	intel_prop->dodse2 = 0x0;

	intel_prop->clds = 0x0;

	intel_prop->clss = 0x0;

	intel_prop->doaise = 0x1;

	intel_prop->doais = 0x3;

	intel_prop->dodse  = 0x0;

	intel_prop->dods  = 0x1;



	fwnode_property_read_u16(link,

				 "intel-sdw-clde",

				 &intel_prop->clde);

	fwnode_property_read_u16(link,

				 "intel-sdw-doaise2",

				 &intel_prop->doaise2);

	fwnode_property_read_u16(link,

				 "intel-sdw-dodse2",

				 &intel_prop->dodse2);

	fwnode_property_read_u16(link,

				 "intel-sdw-clds",

				 &intel_prop->clds);

	fwnode_property_read_u16(link,

				 "intel-sdw-clss",

				 &intel_prop->clss);

	fwnode_property_read_u16(link,

				 "intel-sdw-doaise",

				 &intel_prop->doaise);

include/linux/soundwire/sdw_intel.h

+5 −0
Original line number Diff line number Diff line
@@ -182,6 +182,11 @@ 
#define SDW_SHIM2_INTEL_VS_ACTMCTL_DODSE	BIT(2)

#define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS	GENMASK(4, 3)

#define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAISE	BIT(5)

#define SDW_SHIM3_INTEL_VS_ACTMCTL_CLSS		BIT(6)

#define SDW_SHIM3_INTEL_VS_ACTMCTL_CLDS		GENMASK(11, 7)

#define SDW_SHIM3_INTEL_VS_ACTMCTL_DODSE2	GENMASK(13, 12)

#define SDW_SHIM3_INTEL_VS_ACTMCTL_DOAISE2	BIT(14)

#define SDW_SHIM3_INTEL_VS_ACTMCTL_CLDE		BIT(15)



/**

 * struct sdw_intel_stream_params_data: configuration passed during