Commit 9b6e63a7 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

clk: renesas: rzv2h: Add MSTOP support 



Add MSTOP support to control buses for the individual units on RZ/V2H.
Use per-bit (instead of group-based) configuration and atomic counters,
to ensure precise control over individual MSTOP bits, and to prevent
issues with shared dependencies between module clocks.

Co-developed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Co-developed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241213123550.289193-2-biju.das.jz@bp.renesas.com
Link: https://lore.kernel.org/20250102181839.352599-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Link: https://lore.kernel.org/20250102181839.352599-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Link: https://lore.kernel.org/20250102181839.352599-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Link: https://lore.kernel.org/20250102181839.352599-5-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent f9627452

drivers/clk/renesas/r9a09g057-cpg.c

+104 −51
Original line number Diff line number Diff line
@@ -115,57 +115,108 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { 
};



static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {

	DEF_MOD_CRITICAL("icu_0_pclk_i",	CLK_PLLCM33_DIV16, 0, 5, 0, 5),

	DEF_MOD("gtm_0_pclk",			CLK_PLLCM33_DIV16, 4, 3, 2, 3),

	DEF_MOD("gtm_1_pclk",			CLK_PLLCM33_DIV16, 4, 4, 2, 4),

	DEF_MOD("gtm_2_pclk",			CLK_PLLCLN_DIV16, 4, 5, 2, 5),

	DEF_MOD("gtm_3_pclk",			CLK_PLLCLN_DIV16, 4, 6, 2, 6),

	DEF_MOD("gtm_4_pclk",			CLK_PLLCLN_DIV16, 4, 7, 2, 7),

	DEF_MOD("gtm_5_pclk",			CLK_PLLCLN_DIV16, 4, 8, 2, 8),

	DEF_MOD("gtm_6_pclk",			CLK_PLLCLN_DIV16, 4, 9, 2, 9),

	DEF_MOD("gtm_7_pclk",			CLK_PLLCLN_DIV16, 4, 10, 2, 10),

	DEF_MOD("wdt_0_clkp",			CLK_PLLCM33_DIV16, 4, 11, 2, 11),

	DEF_MOD("wdt_0_clk_loco",		CLK_QEXTAL, 4, 12, 2, 12),

	DEF_MOD("wdt_1_clkp",			CLK_PLLCLN_DIV16, 4, 13, 2, 13),

	DEF_MOD("wdt_1_clk_loco",		CLK_QEXTAL, 4, 14, 2, 14),

	DEF_MOD("wdt_2_clkp",			CLK_PLLCLN_DIV16, 4, 15, 2, 15),

	DEF_MOD("wdt_2_clk_loco",		CLK_QEXTAL, 5, 0, 2, 16),

	DEF_MOD("wdt_3_clkp",			CLK_PLLCLN_DIV16, 5, 1, 2, 17),

	DEF_MOD("wdt_3_clk_loco",		CLK_QEXTAL, 5, 2, 2, 18),

	DEF_MOD("scif_0_clk_pck",		CLK_PLLCM33_DIV16, 8, 15, 4, 15),

	DEF_MOD("riic_8_ckm",			CLK_PLLCM33_DIV16, 9, 3, 4, 19),

	DEF_MOD("riic_0_ckm",			CLK_PLLCLN_DIV16, 9, 4, 4, 20),

	DEF_MOD("riic_1_ckm",			CLK_PLLCLN_DIV16, 9, 5, 4, 21),

	DEF_MOD("riic_2_ckm",			CLK_PLLCLN_DIV16, 9, 6, 4, 22),

	DEF_MOD("riic_3_ckm",			CLK_PLLCLN_DIV16, 9, 7, 4, 23),

	DEF_MOD("riic_4_ckm",			CLK_PLLCLN_DIV16, 9, 8, 4, 24),

	DEF_MOD("riic_5_ckm",			CLK_PLLCLN_DIV16, 9, 9, 4, 25),

	DEF_MOD("riic_6_ckm",			CLK_PLLCLN_DIV16, 9, 10, 4, 26),

	DEF_MOD("riic_7_ckm",			CLK_PLLCLN_DIV16, 9, 11, 4, 27),

	DEF_MOD("sdhi_0_imclk",			CLK_PLLCLN_DIV8, 10, 3, 5, 3),

	DEF_MOD("sdhi_0_imclk2",		CLK_PLLCLN_DIV8, 10, 4, 5, 4),

	DEF_MOD("sdhi_0_clk_hs",		CLK_PLLCLN_DIV2, 10, 5, 5, 5),

	DEF_MOD("sdhi_0_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6),

	DEF_MOD("sdhi_1_imclk",			CLK_PLLCLN_DIV8, 10, 7, 5, 7),

	DEF_MOD("sdhi_1_imclk2",		CLK_PLLCLN_DIV8, 10, 8, 5, 8),

	DEF_MOD("sdhi_1_clk_hs",		CLK_PLLCLN_DIV2, 10, 9, 5, 9),

	DEF_MOD("sdhi_1_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10),

	DEF_MOD("sdhi_2_imclk",			CLK_PLLCLN_DIV8, 10, 11, 5, 11),

	DEF_MOD("sdhi_2_imclk2",		CLK_PLLCLN_DIV8, 10, 12, 5, 12),

	DEF_MOD("sdhi_2_clk_hs",		CLK_PLLCLN_DIV2, 10, 13, 5, 13),

	DEF_MOD("sdhi_2_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14),

	DEF_MOD("cru_0_aclk",			CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18),

	DEF_MOD_NO_PM("cru_0_vclk",		CLK_PLLVDO_CRU0, 13, 3, 6, 19),

	DEF_MOD("cru_0_pclk",			CLK_PLLDTY_DIV16, 13, 4, 6, 20),

	DEF_MOD("cru_1_aclk",			CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21),

	DEF_MOD_NO_PM("cru_1_vclk",		CLK_PLLVDO_CRU1, 13, 6, 6, 22),

	DEF_MOD("cru_1_pclk",			CLK_PLLDTY_DIV16, 13, 7, 6, 23),

	DEF_MOD("cru_2_aclk",			CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24),

	DEF_MOD_NO_PM("cru_2_vclk",		CLK_PLLVDO_CRU2, 13, 9, 6, 25),

	DEF_MOD("cru_2_pclk",			CLK_PLLDTY_DIV16, 13, 10, 6, 26),

	DEF_MOD("cru_3_aclk",			CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27),

	DEF_MOD_NO_PM("cru_3_vclk",		CLK_PLLVDO_CRU3, 13, 12, 6, 28),

	DEF_MOD("cru_3_pclk",			CLK_PLLDTY_DIV16, 13, 13, 6, 29),

	DEF_MOD_CRITICAL("icu_0_pclk_i",	CLK_PLLCM33_DIV16, 0, 5, 0, 5,

						BUS_MSTOP_NONE),

	DEF_MOD("gtm_0_pclk",			CLK_PLLCM33_DIV16, 4, 3, 2, 3,

						BUS_MSTOP(5, BIT(10))),

	DEF_MOD("gtm_1_pclk",			CLK_PLLCM33_DIV16, 4, 4, 2, 4,

						BUS_MSTOP(5, BIT(11))),

	DEF_MOD("gtm_2_pclk",			CLK_PLLCLN_DIV16, 4, 5, 2, 5,

						BUS_MSTOP(2, BIT(13))),

	DEF_MOD("gtm_3_pclk",			CLK_PLLCLN_DIV16, 4, 6, 2, 6,

						BUS_MSTOP(2, BIT(14))),

	DEF_MOD("gtm_4_pclk",			CLK_PLLCLN_DIV16, 4, 7, 2, 7,

						BUS_MSTOP(11, BIT(13))),

	DEF_MOD("gtm_5_pclk",			CLK_PLLCLN_DIV16, 4, 8, 2, 8,

						BUS_MSTOP(11, BIT(14))),

	DEF_MOD("gtm_6_pclk",			CLK_PLLCLN_DIV16, 4, 9, 2, 9,

						BUS_MSTOP(11, BIT(15))),

	DEF_MOD("gtm_7_pclk",			CLK_PLLCLN_DIV16, 4, 10, 2, 10,

						BUS_MSTOP(12, BIT(0))),

	DEF_MOD("wdt_0_clkp",			CLK_PLLCM33_DIV16, 4, 11, 2, 11,

						BUS_MSTOP(3, BIT(10))),

	DEF_MOD("wdt_0_clk_loco",		CLK_QEXTAL, 4, 12, 2, 12,

						BUS_MSTOP(3, BIT(10))),

	DEF_MOD("wdt_1_clkp",			CLK_PLLCLN_DIV16, 4, 13, 2, 13,

						BUS_MSTOP(1, BIT(0))),

	DEF_MOD("wdt_1_clk_loco",		CLK_QEXTAL, 4, 14, 2, 14,

						BUS_MSTOP(1, BIT(0))),

	DEF_MOD("wdt_2_clkp",			CLK_PLLCLN_DIV16, 4, 15, 2, 15,

						BUS_MSTOP(5, BIT(12))),

	DEF_MOD("wdt_2_clk_loco",		CLK_QEXTAL, 5, 0, 2, 16,

						BUS_MSTOP(5, BIT(12))),

	DEF_MOD("wdt_3_clkp",			CLK_PLLCLN_DIV16, 5, 1, 2, 17,

						BUS_MSTOP(5, BIT(13))),

	DEF_MOD("wdt_3_clk_loco",		CLK_QEXTAL, 5, 2, 2, 18,

						BUS_MSTOP(5, BIT(13))),

	DEF_MOD("scif_0_clk_pck",		CLK_PLLCM33_DIV16, 8, 15, 4, 15,

						BUS_MSTOP(3, BIT(14))),

	DEF_MOD("riic_8_ckm",			CLK_PLLCM33_DIV16, 9, 3, 4, 19,

						BUS_MSTOP(3, BIT(13))),

	DEF_MOD("riic_0_ckm",			CLK_PLLCLN_DIV16, 9, 4, 4, 20,

						BUS_MSTOP(1, BIT(1))),

	DEF_MOD("riic_1_ckm",			CLK_PLLCLN_DIV16, 9, 5, 4, 21,

						BUS_MSTOP(1, BIT(2))),

	DEF_MOD("riic_2_ckm",			CLK_PLLCLN_DIV16, 9, 6, 4, 22,

						BUS_MSTOP(1, BIT(3))),

	DEF_MOD("riic_3_ckm",			CLK_PLLCLN_DIV16, 9, 7, 4, 23,

						BUS_MSTOP(1, BIT(4))),

	DEF_MOD("riic_4_ckm",			CLK_PLLCLN_DIV16, 9, 8, 4, 24,

						BUS_MSTOP(1, BIT(5))),

	DEF_MOD("riic_5_ckm",			CLK_PLLCLN_DIV16, 9, 9, 4, 25,

						BUS_MSTOP(1, BIT(6))),

	DEF_MOD("riic_6_ckm",			CLK_PLLCLN_DIV16, 9, 10, 4, 26,

						BUS_MSTOP(1, BIT(7))),

	DEF_MOD("riic_7_ckm",			CLK_PLLCLN_DIV16, 9, 11, 4, 27,

						BUS_MSTOP(1, BIT(8))),

	DEF_MOD("sdhi_0_imclk",			CLK_PLLCLN_DIV8, 10, 3, 5, 3,

						BUS_MSTOP(8, BIT(2))),

	DEF_MOD("sdhi_0_imclk2",		CLK_PLLCLN_DIV8, 10, 4, 5, 4,

						BUS_MSTOP(8, BIT(2))),

	DEF_MOD("sdhi_0_clk_hs",		CLK_PLLCLN_DIV2, 10, 5, 5, 5,

						BUS_MSTOP(8, BIT(2))),

	DEF_MOD("sdhi_0_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,

						BUS_MSTOP(8, BIT(2))),

	DEF_MOD("sdhi_1_imclk",			CLK_PLLCLN_DIV8, 10, 7, 5, 7,

						BUS_MSTOP(8, BIT(3))),

	DEF_MOD("sdhi_1_imclk2",		CLK_PLLCLN_DIV8, 10, 8, 5, 8,

						BUS_MSTOP(8, BIT(3))),

	DEF_MOD("sdhi_1_clk_hs",		CLK_PLLCLN_DIV2, 10, 9, 5, 9,

						BUS_MSTOP(8, BIT(3))),

	DEF_MOD("sdhi_1_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,

						BUS_MSTOP(8, BIT(3))),

	DEF_MOD("sdhi_2_imclk",			CLK_PLLCLN_DIV8, 10, 11, 5, 11,

						BUS_MSTOP(8, BIT(4))),

	DEF_MOD("sdhi_2_imclk2",		CLK_PLLCLN_DIV8, 10, 12, 5, 12,

						BUS_MSTOP(8, BIT(4))),

	DEF_MOD("sdhi_2_clk_hs",		CLK_PLLCLN_DIV2, 10, 13, 5, 13,

						BUS_MSTOP(8, BIT(4))),

	DEF_MOD("sdhi_2_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,

						BUS_MSTOP(8, BIT(4))),

	DEF_MOD("cru_0_aclk",			CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,

						BUS_MSTOP(9, BIT(4))),

	DEF_MOD_NO_PM("cru_0_vclk",		CLK_PLLVDO_CRU0, 13, 3, 6, 19,

						BUS_MSTOP(9, BIT(4))),

	DEF_MOD("cru_0_pclk",			CLK_PLLDTY_DIV16, 13, 4, 6, 20,

						BUS_MSTOP(9, BIT(4))),

	DEF_MOD("cru_1_aclk",			CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21,

						BUS_MSTOP(9, BIT(5))),

	DEF_MOD_NO_PM("cru_1_vclk",		CLK_PLLVDO_CRU1, 13, 6, 6, 22,

						BUS_MSTOP(9, BIT(5))),

	DEF_MOD("cru_1_pclk",			CLK_PLLDTY_DIV16, 13, 7, 6, 23,

						BUS_MSTOP(9, BIT(5))),

	DEF_MOD("cru_2_aclk",			CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24,

						BUS_MSTOP(9, BIT(6))),

	DEF_MOD_NO_PM("cru_2_vclk",		CLK_PLLVDO_CRU2, 13, 9, 6, 25,

						BUS_MSTOP(9, BIT(6))),

	DEF_MOD("cru_2_pclk",			CLK_PLLDTY_DIV16, 13, 10, 6, 26,

						BUS_MSTOP(9, BIT(6))),

	DEF_MOD("cru_3_aclk",			CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27,

						BUS_MSTOP(9, BIT(7))),

	DEF_MOD_NO_PM("cru_3_vclk",		CLK_PLLVDO_CRU3, 13, 12, 6, 28,

						BUS_MSTOP(9, BIT(7))),

	DEF_MOD("cru_3_pclk",			CLK_PLLDTY_DIV16, 13, 13, 6, 29,

						BUS_MSTOP(9, BIT(7))),

};



static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
@@ -224,4 +275,6 @@ const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = { 
	/* Resets */

	.resets = r9a09g057_resets,

	.num_resets = ARRAY_SIZE(r9a09g057_resets),



	.num_mstop_bits = 192,

};

drivers/clk/renesas/rzv2h-cpg.c

+125 −21
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
#include <linux/platform_device.h>

#include <linux/pm_clock.h>

#include <linux/pm_domain.h>

#include <linux/refcount.h>

#include <linux/reset-controller.h>



#include <dt-bindings/clock/renesas-cpg-mssr.h>
@@ -40,6 +41,9 @@ 
#define GET_RST_OFFSET(x)	(0x900 + ((x) * 4))

#define GET_RST_MON_OFFSET(x)	(0xA00 + ((x) * 4))



#define CPG_BUS_1_MSTOP		(0xd00)

#define CPG_BUS_MSTOP(m)	(CPG_BUS_1_MSTOP + ((m) - 1) * 4)



#define KDIV(val)		((s16)FIELD_GET(GENMASK(31, 16), (val)))

#define MDIV(val)		FIELD_GET(GENMASK(15, 6), (val))

#define PDIV(val)		FIELD_GET(GENMASK(5, 0), (val))
@@ -64,6 +68,7 @@ 
 * @resets: Array of resets

 * @num_resets: Number of Module Resets in info->resets[]

 * @last_dt_core_clk: ID of the last Core Clock exported to DT

 * @mstop_count: Array of mstop values

 * @rcdev: Reset controller entity

 */

struct rzv2h_cpg_priv {
@@ -78,6 +83,8 @@ struct rzv2h_cpg_priv { 
	unsigned int num_resets;

	unsigned int last_dt_core_clk;



	atomic_t *mstop_count;



	struct reset_controller_dev rcdev;

};
@@ -97,6 +104,7 @@ struct pll_clk { 
 * struct mod_clock - Module clock

 *

 * @priv: CPG private data

 * @mstop_data: mstop data relating to module clock

 * @hw: handle between common and hardware-specific interfaces

 * @no_pm: flag to indicate PM is not supported

 * @on_index: register offset
@@ -106,6 +114,7 @@ struct pll_clk { 
 */

struct mod_clock {

	struct rzv2h_cpg_priv *priv;

	unsigned int mstop_data;

	struct clk_hw hw;

	bool no_pm;

	u8 on_index;
@@ -433,8 +442,71 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core, 
		core->name, PTR_ERR(clk));

}



static void rzv2h_mod_clock_mstop_enable(struct rzv2h_cpg_priv *priv,

					 u32 mstop_data)

{

	unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, mstop_data);

	u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, mstop_data);

	unsigned int index = (mstop_index - 1) * 16;

	atomic_t *mstop = &priv->mstop_count[index];

	unsigned long flags;

	unsigned int i;

	u32 val = 0;



	spin_lock_irqsave(&priv->rmw_lock, flags);

	for_each_set_bit(i, &mstop_mask, 16) {

		if (!atomic_read(&mstop[i]))

			val |= BIT(i) << 16;

		atomic_inc(&mstop[i]);

	}

	if (val)

		writel(val, priv->base + CPG_BUS_MSTOP(mstop_index));

	spin_unlock_irqrestore(&priv->rmw_lock, flags);

}



static void rzv2h_mod_clock_mstop_disable(struct rzv2h_cpg_priv *priv,

					  u32 mstop_data)

{

	unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, mstop_data);

	u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, mstop_data);

	unsigned int index = (mstop_index - 1) * 16;

	atomic_t *mstop = &priv->mstop_count[index];

	unsigned long flags;

	unsigned int i;

	u32 val = 0;



	spin_lock_irqsave(&priv->rmw_lock, flags);

	for_each_set_bit(i, &mstop_mask, 16) {

		if (!atomic_read(&mstop[i]) ||

		    atomic_dec_and_test(&mstop[i]))

			val |= BIT(i) << 16 | BIT(i);

	}

	if (val)

		writel(val, priv->base + CPG_BUS_MSTOP(mstop_index));

	spin_unlock_irqrestore(&priv->rmw_lock, flags);

}



static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)

{

	struct mod_clock *clock = to_mod_clock(hw);

	struct rzv2h_cpg_priv *priv = clock->priv;

	u32 bitmask;

	u32 offset;



	if (clock->mon_index >= 0) {

		offset = GET_CLK_MON_OFFSET(clock->mon_index);

		bitmask = BIT(clock->mon_bit);

	} else {

		offset = GET_CLK_ON_OFFSET(clock->on_index);

		bitmask = BIT(clock->on_bit);

	}



	return readl(priv->base + offset) & bitmask;

}



static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable)

{

	bool enabled = rzv2h_mod_clock_is_enabled(hw);

	struct mod_clock *clock = to_mod_clock(hw);

	unsigned int reg = GET_CLK_ON_OFFSET(clock->on_index);

	struct rzv2h_cpg_priv *priv = clock->priv;
@@ -446,11 +518,20 @@ static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable) 
	dev_dbg(dev, "CLK_ON 0x%x/%pC %s\n", reg, hw->clk,

		enable ? "ON" : "OFF");



	if (enabled == enable)

		return 0;



	value = bitmask << 16;

	if (enable)

	if (enable) {

		value |= bitmask;



		writel(value, priv->base + reg);

		if (clock->mstop_data != BUS_MSTOP_NONE)

			rzv2h_mod_clock_mstop_enable(priv, clock->mstop_data);

	} else {

		if (clock->mstop_data != BUS_MSTOP_NONE)

			rzv2h_mod_clock_mstop_disable(priv, clock->mstop_data);

		writel(value, priv->base + reg);

	}



	if (!enable || clock->mon_index < 0)

		return 0;
@@ -476,24 +557,6 @@ static void rzv2h_mod_clock_disable(struct clk_hw *hw) 
	rzv2h_mod_clock_endisable(hw, false);

}



static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)

{

	struct mod_clock *clock = to_mod_clock(hw);

	struct rzv2h_cpg_priv *priv = clock->priv;

	u32 bitmask;

	u32 offset;



	if (clock->mon_index >= 0) {

		offset = GET_CLK_MON_OFFSET(clock->mon_index);

		bitmask = BIT(clock->mon_bit);

	} else {

		offset = GET_CLK_ON_OFFSET(clock->on_index);

		bitmask = BIT(clock->on_bit);

	}



	return readl(priv->base + offset) & bitmask;

}



static const struct clk_ops rzv2h_mod_clock_ops = {

	.enable = rzv2h_mod_clock_enable,

	.disable = rzv2h_mod_clock_disable,
@@ -546,6 +609,7 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod, 
	clock->no_pm = mod->no_pm;

	clock->priv = priv;

	clock->hw.init = &init;

	clock->mstop_data = mod->mstop_data;



	ret = devm_clk_hw_register(dev, &clock->hw);

	if (ret) {
@@ -555,6 +619,41 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod, 


	priv->clks[id] = clock->hw.clk;



	/*

	 * Ensure the module clocks and MSTOP bits are synchronized when they are

	 * turned ON by the bootloader. Enable MSTOP bits for module clocks that were

	 * turned ON in an earlier boot stage.

	 */

	if (clock->mstop_data != BUS_MSTOP_NONE &&

	    !mod->critical && rzv2h_mod_clock_is_enabled(&clock->hw)) {

		rzv2h_mod_clock_mstop_enable(priv, clock->mstop_data);

	} else if (clock->mstop_data != BUS_MSTOP_NONE && mod->critical) {

		unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, clock->mstop_data);

		u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, clock->mstop_data);

		unsigned int index = (mstop_index - 1) * 16;

		atomic_t *mstop = &priv->mstop_count[index];

		unsigned long flags;

		unsigned int i;

		u32 val = 0;



		/*

		 * Critical clocks are turned ON immediately upon registration, and the

		 * MSTOP counter is updated through the rzv2h_mod_clock_enable() path.

		 * However, if the critical clocks were already turned ON by the initial

		 * bootloader, synchronize the atomic counter here and clear the MSTOP bit.

		 */

		spin_lock_irqsave(&priv->rmw_lock, flags);

		for_each_set_bit(i, &mstop_mask, 16) {

			if (atomic_read(&mstop[i]))

				continue;

			val |= BIT(i) << 16;

			atomic_inc(&mstop[i]);

		}

		if (val)

			writel(val, priv->base + CPG_BUS_MSTOP(mstop_index));

		spin_unlock_irqrestore(&priv->rmw_lock, flags);

	}



	return;



fail:
@@ -822,6 +921,11 @@ static int __init rzv2h_cpg_probe(struct platform_device *pdev) 
	if (!clks)

		return -ENOMEM;



	priv->mstop_count = devm_kcalloc(dev, info->num_mstop_bits,

					 sizeof(*priv->mstop_count), GFP_KERNEL);

	if (!priv->mstop_count)

		return -ENOMEM;



	priv->resets = devm_kmemdup(dev, info->resets, sizeof(*info->resets) *

				    info->num_resets, GFP_KERNEL);

	if (!priv->resets)

drivers/clk/renesas/rzv2h-cpg.h

+23 −7
Original line number Diff line number Diff line
@@ -8,6 +8,8 @@ 
#ifndef __RENESAS_RZV2H_CPG_H__

#define __RENESAS_RZV2H_CPG_H__



#include <linux/bitfield.h>



/**

 * struct ddiv - Structure for dynamic switching divider

 *
@@ -46,6 +48,12 @@ struct ddiv { 
#define CDDIV4_DIVCTL1	DDIV_PACK(CPG_CDDIV4, 4, 1, 17)

#define CDDIV4_DIVCTL2	DDIV_PACK(CPG_CDDIV4, 8, 1, 18)



#define BUS_MSTOP_IDX_MASK	GENMASK(31, 16)

#define BUS_MSTOP_BITS_MASK	GENMASK(15, 0)

#define BUS_MSTOP(idx, mask)	(FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \

				 FIELD_PREP_CONST(BUS_MSTOP_BITS_MASK, (mask)))

#define BUS_MSTOP_NONE		GENMASK(31, 0)



/**

 * Definitions of CPG Core Clocks

 *
@@ -104,6 +112,7 @@ enum clk_types { 
 * struct rzv2h_mod_clk - Module Clocks definitions

 *

 * @name: handle between common and hardware-specific interfaces

 * @mstop_data: packed data mstop register offset and mask

 * @parent: id of parent clock

 * @critical: flag to indicate the clock is critical

 * @no_pm: flag to indicate PM is not supported
@@ -114,6 +123,7 @@ enum clk_types { 
 */

struct rzv2h_mod_clk {

	const char *name;

	u32 mstop_data;

	u16 parent;

	bool critical;

	bool no_pm;
@@ -123,9 +133,10 @@ struct rzv2h_mod_clk { 
	u8 mon_bit;

};



#define DEF_MOD_BASE(_name, _parent, _critical, _no_pm, _onindex, _onbit, _monindex, _monbit) \

#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, _onbit, _monindex, _monbit) \

	{ \

		.name = (_name), \

		.mstop_data = (_mstop), \

		.parent = (_parent), \

		.critical = (_critical), \

		.no_pm = (_no_pm), \
@@ -135,14 +146,14 @@ struct rzv2h_mod_clk { 
		.mon_bit = (_monbit), \

	}



#define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit)		\

	DEF_MOD_BASE(_name, _parent, false, false, _onindex, _onbit, _monindex, _monbit)

#define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \

	DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)



#define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit)	\

	DEF_MOD_BASE(_name, _parent, true, false, _onindex, _onbit, _monindex, _monbit)

#define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \

	DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit)



#define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit)		\

	DEF_MOD_BASE(_name, _parent, false, true, _onindex, _onbit, _monindex, _monbit)

#define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \

	DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit)



/**

 * struct rzv2h_reset - Reset definitions
@@ -184,6 +195,9 @@ struct rzv2h_reset { 
 *

 * @resets: Array of Module Reset definitions

 * @num_resets: Number of entries in resets[]

 *

 * @num_mstop_bits: Maximum number of MSTOP bits supported, equivalent to the

 *		    number of CPG_BUS_m_MSTOP registers multiplied by 16.

 */

struct rzv2h_cpg_info {

	/* Core Clocks */
@@ -200,6 +214,8 @@ struct rzv2h_cpg_info { 
	/* Resets */

	const struct rzv2h_reset *resets;

	unsigned int num_resets;



	unsigned int num_mstop_bits;

};



extern const struct rzv2h_cpg_info r9a09g057_cpg_info;