Commit 9b725d59 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'phy-for-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy 

Pull phy updates from Vinod Koul:
 "Core:

   - Add suuport for "rx-polarity" and "tx-polarity" device tree
     properties and phy common properties to manage this

  New Support:

   - Qualcomm Glymur PCIe Gen4 2-lanes PCIe phy, DP and edp phy, USB UNI
     PHY and SMB2370 eUSB2 repeater. SC8280xp QMP UFS PHY, Kaanapali
     PCIe phy and QMP PHY, QCS615 QMP USB3+DP PHY and driver support for
     that.

   - SpacemiT PCIe/combo PHY and K1 USB2 PHY driver.

   - HDMI 2.1 FRL configuration support and driver enabling for rockchip
     samsung-hdptx driver

   - TI TCAN1046 phy

   - Renesas RZ/V2H(P) and RZ/V2N usb3

   - Mediatek MT8188 hdmi-phy

   - Google Tensor SoC USB PHY driver

   - Apple Type-C PHY

  Updates:

   - Subsystem conversion for clock round_rate() to determine_rate()

   - TI USB3 DT schema conversion

   - Samsung ExynosAutov920 usb3, combo hsphy and ssphy support"

* tag 'phy-for-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (143 commits)
  phy: ti: phy-j721e-wiz: convert from divider_round_rate() to divider_determine_rate()
  dt-bindings: phy: ti,control-phy-otghs: convert to DT schema
  dt-bindings: phy: ti,phy-usb3: convert to DT schema
  phy: tegra: xusb: Remove unused powered_on variable
  phy: renesas: rcar-gen3-usb2: add regulator dependency
  phy: GOOGLE_USB: add TYPEC dependency
  phy: enter drivers/phy/Makefile even without CONFIG_GENERIC_PHY
  phy: renesas: rcar-gen3-usb2: Use mux-state for phyrst management
  phy: renesas: rcar-gen3-usb2: Add regulator for OTG VBUS control
  phy: renesas: rcar-gen3-usb2: Use devm_pm_runtime_enable()
  phy: renesas: rcar-gen3-usb2: Factor out VBUS control logic
  dt-bindings: phy: renesas,usb2-phy: Document RZ/G3E SoC
  dt-bindings: phy: renesas,usb2-phy: Document mux-states property
  dt-bindings: phy: renesas,usb2-phy: Document USB VBUS regulator
  phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL support
  phy: rockchip: samsung-hdptx: Extend rk_hdptx_phy_verify_hdmi_config() helper
  phy: rockchip: samsung-hdptx: Switch to driver specific HDMI config
  phy: rockchip: samsung-hdptx: Drop hw_rate driver data
  phy: rockchip: samsung-hdptx: Compute clk rate from PLL config
  phy: rockchip: samsung-hdptx: Cleanup *_cmn_init_seq lists
  ...
parents 4e15e819 dbeea86f

Documentation/devicetree/bindings/phy/apple,atcphy.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/apple,atcphy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Apple Type-C PHY (ATCPHY)



maintainers:

  - Sven Peter <sven@kernel.org>



description: >

  The Apple Type-C PHY (ATCPHY) is a combined PHY for USB 2.0, USB 3.x,

  USB4/Thunderbolt, and DisplayPort connectivity via Type-C ports found in

  Apple Silicon SoCs.



  The PHY handles muxing between these different protocols and also provides the

  reset controller for the attached DWC3 USB controller.



  It is designed for USB4 operation and does not handle individual differential

  pairs as distinct DisplayPort lanes. Any reference to lane in this binding

  hence refers to two differential pairs (RX and TX) as used in USB terminology.



  In order to correctly setup these lanes for the various modes calibration

  values copied from Apple's firmware and converted to the format described

  below by our bootloader m1n1 are required. Without these only USB2 operation

  is possible.



allOf:

  - $ref: /schemas/usb/usb-switch.yaml#



$defs:

  apple,tunable:

    $ref: /schemas/types.yaml#/definitions/uint32-matrix

    items:

      items:

        - description: Register offset

        - description: Mask to be applied to the register value

        - description: Bits to be set after applying the mask

    description: >

      List of (register offset, mask, value) tuples copied from Apple's Device

      Tree by our bootloader m1n1 and used to configure the PHY. These values

      even vary for a single product/device and likely contain calibration

      values determined by Apple at manufacturing time.

      Unless otherwise noted these tunables are always applied to the core

      register region.



properties:

  compatible:

    oneOf:

      - items:

          - enum:

              - apple,t6000-atcphy

              - apple,t6020-atcphy

              - apple,t8112-atcphy

          - const: apple,t8103-atcphy

      - const: apple,t8103-atcphy



  reg:

    items:

      - description: Common controls for all PHYs (USB2/3/4, DisplayPort, TBT)

      - description: DisplayPort Alternate Mode PHY specific controls

      - description: Type-C PHY AXI to Apple Fabric interconnect controls

      - description: USB2 PHY specific controls

      - description: USB3 PIPE interface controls



  reg-names:

    items:

      - const: core

      - const: lpdptx

      - const: axi2af

      - const: usb2phy

      - const: pipehandler



  "#phy-cells":

    const: 1



  "#reset-cells":

    const: 0



  mode-switch: true

  orientation-switch: true



  power-domains:

    maxItems: 1



  ports:

    $ref: /schemas/graph.yaml#/properties/ports

    properties:

      port@0:

        $ref: /schemas/graph.yaml#/properties/port

        description: Outgoing connection to the SS port of the Type-C connector.



      port@1:

        $ref: /schemas/graph.yaml#/properties/port

        description: Incoming endpoint from the USB3 controller.



      port@2:

        $ref: /schemas/graph.yaml#/properties/port

        description: Incoming endpoint from the DisplayPort controller.



      port@3:

        $ref: /schemas/graph.yaml#/properties/port

        description: Incoming endpoint from the USB4/Thunderbolt controller.



  apple,tunable-common-a:

    $ref: "#/$defs/apple,tunable"

    description: >

      Common tunables required for all modes, applied before tunable-axi2af.



  apple,tunable-axi2af:

    $ref: "#/$defs/apple,tunable"

    description: >

      AXI to Apple Fabric tunables, required for all modes. Unlike all other

      tunables these are applied to the axi2af region.



  apple,tunable-common-b:

    $ref: "#/$defs/apple,tunable"

    description: >

      Common tunables required for all modes, applied after tunable-axi2af.



  apple,tunable-lane0-usb:

    $ref: "#/$defs/apple,tunable"

    description: USB3 tunables for lane 0.



  apple,tunable-lane1-usb:

    $ref: "#/$defs/apple,tunable"

    description: USB3 tunables for lane 1.



  apple,tunable-lane0-cio:

    $ref: "#/$defs/apple,tunable"

    description: USB4/Thunderbolt ("Converged IO") tunables for lane 0.



  apple,tunable-lane1-cio:

    $ref: "#/$defs/apple,tunable"

    description: USB4/Thunderbolt ("Converged IO") tunables for lane 1.



  apple,tunable-lane0-dp:

    $ref: "#/$defs/apple,tunable"

    description: >

      DisplayPort tunables for lane 0.



      Note that lane here refers to a USB RX and TX pair re-used for DisplayPort

      and not to an individual DisplayPort differential lane.



  apple,tunable-lane1-dp:

    $ref: "#/$defs/apple,tunable"

    description: >

      DisplayPort tunables for lane 1.



      Note that lane here refers to a USB RX and TX pair re-used for DisplayPort

      and not to an individual DisplayPort differential lane.



required:

  - compatible

  - reg

  - reg-names

  - "#phy-cells"

  - "#reset-cells"

  - orientation-switch

  - mode-switch

  - power-domains

  - ports



additionalProperties: false



examples:

  - |

    phy@83000000 {

      compatible = "apple,t8103-atcphy";

      reg = <0x83000000 0x4c000>,

            <0x83050000 0x8000>,

            <0x80000000 0x4000>,

            <0x82a90000 0x4000>,

            <0x82a84000 0x4000>;

      reg-names = "core", "lpdptx", "axi2af", "usb2phy",

                  "pipehandler";



      #phy-cells = <1>;

      #reset-cells = <0>;



      orientation-switch;

      mode-switch;

      power-domains = <&ps_atc0_usb>;



      ports {

        #address-cells = <1>;

        #size-cells = <0>;



        port@0 {

          reg = <0>;



          endpoint {

            remote-endpoint = <&typec_connector_ss>;

          };

        };



        port@1 {

          reg = <1>;



          endpoint {

            remote-endpoint = <&dwc3_ss_out>;

          };

        };



        port@2 {

          reg = <2>;



          endpoint {

            remote-endpoint = <&dcp_dp_out>;

          };

        };



        port@3 {

          reg = <3>;



          endpoint {

            remote-endpoint = <&acio_tbt_out>;

          };

        };

      };

    };

Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml

+70 −1
Original line number Diff line number Diff line
@@ -20,6 +20,32 @@ properties: 
  "#phy-cells":

    const: 1



  "#address-cells":

    const: 1



  "#size-cells":

    const: 0



patternProperties:

  "^phy@[0-7]$":

    type: object

    description: SerDes lane (single RX/TX differential pair)



    properties:

      reg:

        minimum: 0

        maximum: 7

        description: Lane index as seen in register map



      "#phy-cells":

        const: 0



    required:

      - reg

      - "#phy-cells"



    additionalProperties: false



required:

  - compatible

  - reg
@@ -32,9 +58,52 @@ examples: 
    soc {

      #address-cells = <2>;

      #size-cells = <2>;

      serdes_1: phy@1ea0000 {



      serdes@1ea0000 {

        compatible = "fsl,lynx-28g";

        reg = <0x0 0x1ea0000 0x0 0x1e30>;

        #address-cells = <1>;

        #size-cells = <0>;

        #phy-cells = <1>;



        phy@0 {

          reg = <0>;

          #phy-cells = <0>;

        };



        phy@1 {

          reg = <1>;

          #phy-cells = <0>;

        };



        phy@2 {

          reg = <2>;

          #phy-cells = <0>;

        };



        phy@3 {

          reg = <3>;

          #phy-cells = <0>;

        };



        phy@4 {

          reg = <4>;

          #phy-cells = <0>;

        };



        phy@5 {

          reg = <5>;

          #phy-cells = <0>;

        };



        phy@6 {

          reg = <6>;

          #phy-cells = <0>;

        };



        phy@7 {

          reg = <7>;

          #phy-cells = <0>;

        };

      };

    };

Documentation/devicetree/bindings/phy/google,lga-usb-phy.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

# Copyright (C) 2025, Google LLC

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/google,lga-usb-phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Google Tensor Series G5 (Laguna) USB PHY



maintainers:

  - Roy Luo <royluo@google.com>



description:

  Describes the USB PHY interfaces integrated with the DWC3 USB controller on

  Google Tensor SoCs, starting with the G5 generation (laguna).

  Two specific PHY IPs from Synopsys are integrated, including eUSB 2.0 PHY IP

  and USB3.2/DisplayPort combo PHY IP.



properties:

  compatible:

    const: google,lga-usb-phy



  reg:

    items:

      - description: USB3.2/DisplayPort combo PHY core registers.

      - description: USB3.2/DisplayPort combo PHY Type-C Assist registers.

      - description: eUSB 2.0 PHY core registers.

      - description: Top-level wrapper registers for the integrated PHYs.



  reg-names:

    items:

      - const: usb3_core

      - const: usb3_tca

      - const: usb2_core

      - const: usbdp_top



  "#phy-cells":

    description: |

      The phandle's argument in the PHY specifier selects one of the three

      following PHY interfaces.

      - 0 for USB high-speed.

      - 1 for USB super-speed.

      - 2 for DisplayPort.

    const: 1



  clocks:

    items:

      - description: USB2 PHY clock.

      - description: USB2 PHY APB clock.

      - description: USB3.2/DisplayPort combo PHY clock.

      - description: USB3.2/DisplayPort combo PHY firmware clock.



  clock-names:

    items:

      - const: usb2

      - const: usb2_apb

      - const: usb3

      - const: usb3_fw



  resets:

    items:

      - description: USB2 PHY reset.

      - description: USB2 PHY APB reset.

      - description: USB3.2/DisplayPort combo PHY reset.



  reset-names:

    items:

      - const: usb2

      - const: usb2_apb

      - const: usb3



  power-domains:

    maxItems: 1



  orientation-switch:

    type: boolean

    description:

      Indicates the PHY as a handler of USB Type-C orientation changes



  google,usb-cfg-csr:

    description:

      A phandle to a syscon node used to access the USB configuration

      registers. These registers are the top-level wrapper of the USB

      subsystem and provide control and status for the integrated USB

      controller and USB PHY.

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

      - items:

          - description: phandle to the syscon node.

          - description: USB2 PHY configuration register offset.



required:

  - compatible

  - reg

  - reg-names

  - "#phy-cells"

  - clocks

  - clock-names

  - resets

  - reset-names

  - power-domains

  - orientation-switch

  - google,usb-cfg-csr



additionalProperties: false



examples:

  - |

    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        usb-phy@c410000 {

            compatible = "google,lga-usb-phy";

            reg = <0 0x0c410000 0 0x20000>,

                  <0 0x0c430000 0 0x1000>,

                  <0 0x0c440000 0 0x10000>,

                  <0 0x0c637000 0 0xa0>;

            reg-names = "usb3_core", "usb3_tca", "usb2_core", "usbdp_top";

            #phy-cells = <1>;

            clocks = <&hsion_usb2_phy_clk>, <&hsion_u2phy_apb_clk>,

                     <&hsion_usb3_phy_clk>, <&hsion_usb3_phy_fw_clk>;

            clock-names = "usb2", "usb2_apb", "usb3", "usb3_fw";

            resets = <&hsion_resets_usb2_phy>,

                     <&hsion_resets_u2phy_apb>,

                     <&hsion_resets_usb3_phy>;

            reset-names = "usb2", "usb2_apb", "usb3";

            power-domains = <&hsio_n_usb_pd>;

            orientation-switch;

            google,usb-cfg-csr = <&usb_cfg_csr 0x14>;

        };

    };

...

Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml

+29 −1
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@@ -18,6 +18,7 @@ properties: 
  compatible:

    oneOf:

      - enum:

          - qcom,glymur-dp-phy

          - qcom,sa8775p-edp-phy

          - qcom,sc7280-edp-phy

          - qcom,sc8180x-edp-phy
@@ -37,12 +38,15 @@ properties: 
      - description: PLL register block



  clocks:

    maxItems: 2

    minItems: 2

    maxItems: 3



  clock-names:

    minItems: 2

    items:

      - const: aux

      - const: cfg_ahb

      - const: ref



  "#clock-cells":

    const: 1
@@ -64,6 +68,30 @@ required: 
  - "#clock-cells"

  - "#phy-cells"



allOf:

  - if:

      properties:

        compatible:

          enum:

            - qcom,glymur-dp-phy

            - qcom,x1e80100-dp-phy

    then:

      properties:

        clocks:

          minItems: 3

          maxItems: 3

        clock-names:

          minItems: 3

          maxItems: 3

    else:

      properties:

        clocks:

          minItems: 2

          maxItems: 2

        clock-names:

          minItems: 2

          maxItems: 2



additionalProperties: false



examples:

Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml

+7 −3
Original line number Diff line number Diff line
@@ -15,9 +15,13 @@ description: 


properties:

  compatible:

    items:

    oneOf:

      - items:

          - enum:

          - qcom,sm8750-m31-eusb2-phy

              - qcom,glymur-m31-eusb2-phy

              - qcom,kaanapali-m31-eusb2-phy

          - const: qcom,sm8750-m31-eusb2-phy

      - const: qcom,sm8750-m31-eusb2-phy



  reg:

    maxItems: 1