Commit 9bb5ca46 authored by Luca Weiss's avatar Luca Weiss Committed by Bjorn Andersson
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arm64: dts: qcom: sm8650: Fix domain-idle-state for CPU2 



On SM8650 the CPUs 0-1 are "silver" (Cortex-A520), CPU 2-6 are "gold"
(Cortex-A720) and CPU 7 is "gold-plus" (Cortex-X4).

So reference the correct "gold" idle-state for CPU core 2.

Fixes: d2350377 ("arm64: dts: qcom: add initial SM8650 dtsi")
Signed-off-by: default avatarLuca Weiss <luca.weiss@fairphone.com>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250314-sm8650-cpu2-sleep-v1-1-31d5c7c87a5d@fairphone.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent cc13a858

arch/arm64/boot/dts/qcom/sm8650.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -1608,7 +1608,7 @@ cpu_pd1: power-domain-cpu1 { 
		cpu_pd2: power-domain-cpu2 {

			#power-domain-cells = <0>;

			power-domains = <&cluster_pd>;

			domain-idle-states = <&silver_cpu_sleep_0>;

			domain-idle-states = <&gold_cpu_sleep_0>;

		};



		cpu_pd3: power-domain-cpu3 {