Commit 9bb95650 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'riscv-for-linus-6.18-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Paul Walmsley:

 - Close a race during boot between userspace vDSO usage and some
   late-initialized vDSO data

 - Improve performance on systems with non-CPU-cache-coherent
   DMA-capable peripherals by enabling write combining on
   pgprot_dmacoherent() allocations

 - Add human-readable detail for RISC-V IPI tracing

 - Provide more information to zsmalloc on 64-bit RISC-V to improve
   allocation

 - Silence useless boot messages about CPUs that have been disabled in
   DT

 - Resolve some compiler and smatch warnings and remove a redundant
   macro

* tag 'riscv-for-linus-6.18-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: hwprobe: avoid uninitialized variable use in hwprobe_arch_id()
  riscv: cpufeature: avoid uninitialized variable in has_thead_homogeneous_vlenb()
  riscv: hwprobe: Fix stale vDSO data for late-initialized keys at boot
  riscv: add a forward declaration for cpuinfo_op
  RISC-V: Don't print details of CPUs disabled in DT
  riscv: Remove the PER_CPU_OFFSET_SHIFT macro
  riscv: mm: Define MAX_POSSIBLE_PHYSMEM_BITS for zsmalloc
  riscv: Register IPI IRQs with unique names
  ACPI: RIMT: Fix unused function warnings when CONFIG_IOMMU_API is disabled
  RISC-V: Define pgprot_dmacoherent() for non-coherent devices
parents 27c0b5c4 b7776a80
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+1 −7
Original line number Diff line number Diff line
@@ -84,15 +84,9 @@
.endm

#ifdef CONFIG_SMP
#ifdef CONFIG_32BIT
#define PER_CPU_OFFSET_SHIFT 2
#else
#define PER_CPU_OFFSET_SHIFT 3
#endif

.macro asm_per_cpu dst sym tmp
	lw    \tmp, TASK_TI_CPU_NUM(tp)
	slli  \tmp, \tmp, PER_CPU_OFFSET_SHIFT
	slli  \tmp, \tmp, RISCV_LGPTR
	la    \dst, __per_cpu_offset
	add   \dst, \dst, \tmp
	REG_L \tmp, 0(\dst)
+2 −0
Original line number Diff line number Diff line
@@ -31,6 +31,8 @@ struct riscv_isainfo {

DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);

extern const struct seq_operations cpuinfo_op;

/* Per-cpu ISA extensions. */
extern struct riscv_isainfo hart_isa[NR_CPUS];

+7 −0
Original line number Diff line number Diff line
@@ -42,4 +42,11 @@ static inline bool riscv_hwprobe_pair_cmp(struct riscv_hwprobe *pair,
	return pair->value == other_pair->value;
}

#ifdef CONFIG_MMU
void riscv_hwprobe_register_async_probe(void);
void riscv_hwprobe_complete_async_probe(void);
#else
static inline void riscv_hwprobe_register_async_probe(void) {}
static inline void riscv_hwprobe_complete_async_probe(void) {}
#endif
#endif
+2 −0
Original line number Diff line number Diff line
@@ -69,6 +69,8 @@ typedef struct {

#define PTRS_PER_PMD    (PAGE_SIZE / sizeof(pmd_t))

#define MAX_POSSIBLE_PHYSMEM_BITS 56

/*
 * rv64 PTE format:
 * | 63 | 62 61 | 60 54 | 53  10 | 9             8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
+2 −0
Original line number Diff line number Diff line
@@ -654,6 +654,8 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
	return __pgprot(prot);
}

#define pgprot_dmacoherent pgprot_writecombine

/*
 * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By
 * default the M-mode firmware enables the hardware updating scheme when only Svadu is present in
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