Commit 9bd110ab authored by Daniel Miess's avatar Daniel Miess Committed by Alex Deucher
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drm/amd/display: Fix TMDS 4K@60Hz YCbCr420 corruption issue 



[Why]
DIG_FIFO_OUTPUT_PIXEL_MODE not being set for dcn314
resulting in incorrect timing for YCbCr4:2:0

[How]
Copy the implementation of set_pixels_per_cycle from dcn32
over to dcn314

Reviewed-by: default avatarNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: default avatarTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: default avatarDaniel Miess <Daniel.Miess@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0cd34ce8

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c

+28 −0
Original line number Diff line number Diff line
@@ -374,3 +374,31 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsig 


	return odm_combine_factor;

}



void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)

{

	uint32_t pix_per_cycle = 1;

	uint32_t odm_combine_factor = 1;



	if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc)

		return;



	odm_combine_factor = get_odm_config(pipe_ctx, NULL);

	if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1

		|| dcn314_is_dp_dig_pixel_rate_div_policy(pipe_ctx))

		pix_per_cycle = 2;



	if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode)

		pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc,

				pix_per_cycle);

}



bool dcn314_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)

{

	struct dc *dc = pipe_ctx->stream->ctx->dc;



	if (dc_is_dp_signal(pipe_ctx->stream->signal) && !is_dp_128b_132b_signal(pipe_ctx) &&

		dc->debug.enable_dp_dig_pixel_rate_div_policy)

		return true;

	return false;

}

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h

+4 −0
Original line number Diff line number Diff line
@@ -39,4 +39,8 @@ void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable); 


unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);



void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);



bool dcn314_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);



#endif /* __DC_HWSS_DCN314_H__ */

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c

+2 −0
Original line number Diff line number Diff line
@@ -145,6 +145,8 @@ static const struct hwseq_private_funcs dcn314_private_funcs = { 
	.set_shaper_3dlut = dcn20_set_shaper_3dlut,

	.setup_hpo_hw_control = dcn31_setup_hpo_hw_control,

	.calculate_dccg_k1_k2_values = dcn314_calculate_dccg_k1_k2_values,

	.set_pixels_per_cycle = dcn314_set_pixels_per_cycle,

	.is_dp_dig_pixel_rate_div_policy = dcn314_is_dp_dig_pixel_rate_div_policy,

};



void dcn314_hw_sequencer_construct(struct dc *dc)