Commit 9bd405c4 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Conor Dooley
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cache: ax45mp_cache: Align end size to cache boundary in ax45mp_dma_cache_wback() 



Align the end size to cache boundary size in ax45mp_dma_cache_wback()
callback likewise done in ax45mp_dma_cache_inv() callback.

Additionally return early in case of start == end.

Fixes: d34599bc ("cache: Add L2 cache management for Andes AX45MP RISC-V core")
Reported-by: default avatarPavel Machek <pavel@denx.de>
Link: https://lore.kernel.org/cip-dev/ZYsdKDiw7G+kxQ3m@duo.ucw.cz/


Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 6613476e

drivers/cache/ax45mp_cache.c

+4 −0
Original line number Diff line number Diff line
@@ -129,8 +129,12 @@ static void ax45mp_dma_cache_wback(phys_addr_t paddr, size_t size) 
	unsigned long line_size;

	unsigned long flags;



	if (unlikely(start == end))

		return;



	line_size = ax45mp_priv.ax45mp_cache_line_size;

	start = start & (~(line_size - 1));

	end = ((end + line_size - 1) & (~(line_size - 1)));

	local_irq_save(flags);

	ax45mp_cpu_dcache_wb_range(start, end);

	local_irq_restore(flags);