Commit 9bd5726f authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v6.9-tag2' of... 

Merge tag 'renesas-clk-for-v6.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull more Renesas clk driver updates from Geert Uytterhoeven:

 - Add Ethernet, SDHI, DMA, and HyperFLASH/QSPI (RPC-IF) clocks on
   R-Car V4M
 - Miscellaneous fixes and improvements

* tag 'renesas-clk-for-v6.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a779h0: Add RPC-IF clock
  clk: renesas: r8a779h0: Add SYS-DMAC clocks
  clk: renesas: r8a779h0: Add SDHI clock
  clk: renesas: r8a779h0: Add EtherAVB clocks
  clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable
  clk: renesas: r9a07g04[34]: Use SEL_SDHI1_STS status configuration for SD1 mux
  clk: renesas: r8a779f0: Correct PFC/GPIO parent clock
  clk: renesas: r8a779g0: Correct PFC/GPIO parent clocks
parents a24f93f1 81a7a88a

drivers/clk/renesas/r8a779f0-cpg-mssr.c

+1 −1
Original line number Diff line number Diff line
@@ -161,7 +161,7 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { 
	DEF_MOD("cmt1",		911,	R8A779F0_CLK_R),

	DEF_MOD("cmt2",		912,	R8A779F0_CLK_R),

	DEF_MOD("cmt3",		913,	R8A779F0_CLK_R),

	DEF_MOD("pfc0",		915,	R8A779F0_CLK_CL16M),

	DEF_MOD("pfc0",		915,	R8A779F0_CLK_CPEX),

	DEF_MOD("tsc",		919,	R8A779F0_CLK_CL16M),

	DEF_MOD("rswitch2",	1505,	R8A779F0_CLK_RSW2),

	DEF_MOD("ether-serdes",	1506,	R8A779F0_CLK_S0D2_HSC),

drivers/clk/renesas/r8a779g0-cpg-mssr.c

+6 −5
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ 


enum clk_ids {

	/* Core Clock Outputs exported to DT */

	LAST_DT_CORE_CLK = R8A779G0_CLK_R,

	LAST_DT_CORE_CLK = R8A779G0_CLK_CP,



	/* External Input Clocks */

	CLK_EXTAL,
@@ -141,6 +141,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { 
	DEF_FIXED("svd2_vip",	R8A779G0_CLK_SVD2_VIP,	CLK_SV_VIP,	2, 1),

	DEF_FIXED("cbfusa",	R8A779G0_CLK_CBFUSA,	CLK_EXTAL,	2, 1),

	DEF_FIXED("cpex",	R8A779G0_CLK_CPEX,	CLK_EXTAL,	2, 1),

	DEF_FIXED("cp",		R8A779G0_CLK_CP,	CLK_EXTAL,	2, 1),

	DEF_FIXED("viobus",	R8A779G0_CLK_VIOBUS,	CLK_VIO,	1, 1),

	DEF_FIXED("viobusd2",	R8A779G0_CLK_VIOBUSD2,	CLK_VIO,	2, 1),

	DEF_FIXED("vcbus",	R8A779G0_CLK_VCBUS,	CLK_VC,		1, 1),
@@ -232,10 +233,10 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { 
	DEF_MOD("cmt1",		911,	R8A779G0_CLK_R),

	DEF_MOD("cmt2",		912,	R8A779G0_CLK_R),

	DEF_MOD("cmt3",		913,	R8A779G0_CLK_R),

	DEF_MOD("pfc0",		915,	R8A779G0_CLK_CL16M),

	DEF_MOD("pfc1",		916,	R8A779G0_CLK_CL16M),

	DEF_MOD("pfc2",		917,	R8A779G0_CLK_CL16M),

	DEF_MOD("pfc3",		918,	R8A779G0_CLK_CL16M),

	DEF_MOD("pfc0",		915,	R8A779G0_CLK_CP),

	DEF_MOD("pfc1",		916,	R8A779G0_CLK_CP),

	DEF_MOD("pfc2",		917,	R8A779G0_CLK_CP),

	DEF_MOD("pfc3",		918,	R8A779G0_CLK_CP),

	DEF_MOD("tsc",		919,	R8A779G0_CLK_CL16M),

	DEF_MOD("tsn",		2723,	R8A779G0_CLK_S0D4_HSC),

	DEF_MOD("ssiu",		2926,	R8A779G0_CLK_S0D6_PER),

drivers/clk/renesas/r8a779h0-cpg-mssr.c

+7 −0
Original line number Diff line number Diff line
@@ -173,6 +173,9 @@ static const struct cpg_core_clk r8a779h0_core_clks[] = { 
};



static const struct mssr_mod_clk r8a779h0_mod_clks[] = {

	DEF_MOD("avb0:rgmii0",	211,	R8A779H0_CLK_S0D8_HSC),

	DEF_MOD("avb1:rgmii1",	212,	R8A779H0_CLK_S0D8_HSC),

	DEF_MOD("avb2:rgmii2",	213,	R8A779H0_CLK_S0D8_HSC),

	DEF_MOD("hscif0",	514,	R8A779H0_CLK_SASYNCPERD1),

	DEF_MOD("hscif1",	515,	R8A779H0_CLK_SASYNCPERD1),

	DEF_MOD("hscif2",	516,	R8A779H0_CLK_SASYNCPERD1),
@@ -181,6 +184,10 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = { 
	DEF_MOD("i2c1",		519,	R8A779H0_CLK_S0D6_PER),

	DEF_MOD("i2c2",		520,	R8A779H0_CLK_S0D6_PER),

	DEF_MOD("i2c3",		521,	R8A779H0_CLK_S0D6_PER),

	DEF_MOD("rpc-if",	629,	R8A779H0_CLK_RPCD2),

	DEF_MOD("sdhi0",	706,	R8A779H0_CLK_SD0),

	DEF_MOD("sydm1",	709,	R8A779H0_CLK_S0D6_PER),

	DEF_MOD("sydm2",	710,	R8A779H0_CLK_S0D6_PER),

	DEF_MOD("wdt1:wdt0",	907,	R8A779H0_CLK_R),

	DEF_MOD("pfc0",		915,	R8A779H0_CLK_CP),

	DEF_MOD("pfc1",		916,	R8A779H0_CLK_CP),

drivers/clk/renesas/r9a07g043-cpg.c

+3 −3
Original line number Diff line number Diff line
@@ -88,7 +88,7 @@ static const struct clk_div_table dtable_1_32[] = { 
/* Mux clock tables */

static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };

static const char * const sel_pll6_2[]	= { ".pll6_250", ".pll5_250" };

static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };

static const char * const sel_sdhi[] = { ".clk_533", ".clk_400", ".clk_266" };



static const u32 mtable_sdhi[] = { 1, 2, 3 };
@@ -137,9 +137,9 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { 
	DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2),

	DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),

	DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),

	DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_shdi,

	DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_sdhi,

		   mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),

	DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, SEL_SDHI0_STS, sel_shdi,

	DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, SEL_SDHI1_STS, sel_sdhi,

		   mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),

	DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G043_CLK_SD0, 1, 4),

	DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G043_CLK_SD1, 1, 4),

drivers/clk/renesas/r9a07g044-cpg.c

+3 −3
Original line number Diff line number Diff line
@@ -106,7 +106,7 @@ static const struct clk_div_table dtable_16_128[] = { 
static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };

static const char * const sel_pll5_4[] = { ".pll5_foutpostdiv", ".pll5_fout1ph0" };

static const char * const sel_pll6_2[]	= { ".pll6_250", ".pll5_250" };

static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };

static const char * const sel_sdhi[] = { ".clk_533", ".clk_400", ".clk_266" };

static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };



static const u32 mtable_sdhi[] = { 1, 2, 3 };
@@ -176,9 +176,9 @@ static const struct { 
		DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, sel_pll6_2),

		DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),

		DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),

		DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_shdi,

		DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_sdhi,

			   mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),

		DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, SEL_SDHI0_STS, sel_shdi,

		DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, SEL_SDHI1_STS, sel_sdhi,

			   mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),

		DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),

		DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),