Commit 9be60113 authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: Use DRAM speed from validation for dummy p-state 



[Description]
When choosing which dummy p-state latency to use, we
need to use the DRAM speed from validation. The DRAMSpeed
DML variable can change because we use different input
params to DML when populating watermarks set B.

Cc: stable@vger.kernel.org # 6.1+
Reviewed-by: default avatarSamson Tam <samson.tam@amd.com>
Acked-by: default avatarHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6f395ceb

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+2 −1
Original line number Diff line number Diff line
@@ -2235,6 +2235,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, 
	int i, pipe_idx, vlevel_temp = 0;

	double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz;

	double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];

	double dram_speed_from_validation = context->bw_ctx.dml.vba.DRAMSpeed;

	double dcfclk_from_fw_based_mclk_switching = dcfclk_from_validation;

	bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] !=

			dm_dram_clock_change_unsupported;
@@ -2422,7 +2423,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, 
	}



	if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {

		min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;

		min_dram_speed_mts = dram_speed_from_validation;

		min_dram_speed_mts_margin = 160;



		context->bw_ctx.dml.soc.dram_clock_change_latency_us =