Commit 9bed716f authored by Pratap Nirujogi's avatar Pratap Nirujogi Committed by Alex Deucher
Browse files

drm/amd/pm: Add support to set min ISP clocks 



Add support to set ISP clocks for SMU v14.0.0. ISP driver
uses amdgpu_dpm_set_soft_freq_range() API to set clocks via
SMU interface than communicating with PMFW directly.

amdgpu_dpm_set_soft_freq_range() is updated to take in any
pp_clock_type than limiting to support only PP_SCLK to allow
ISP and other driver modules to set the min/max clocks. Any
clock specific restrictions are expected to be taken care in
SOC specific SMU implementations instead of generic amdgpu_dpm
and amdgpu_smu interfaces.

Reviewed-by: default avatarXiaojian Du <xiaojian.du@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarMario Limonciello <mario.limonciello@amd.com>
Signed-off-by: default avatarPratap Nirujogi <pratap.nirujogi@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fba8d147

drivers/gpu/drm/amd/include/kgd_pp_interface.h

+2 −0
Original line number Diff line number Diff line
@@ -108,6 +108,8 @@ enum pp_clock_type { 
	PP_VCLK1,

	PP_DCLK,

	PP_DCLK1,

	PP_ISPICLK,

	PP_ISPXCLK,

	OD_SCLK,

	OD_MCLK,

	OD_VDDC_CURVE,

drivers/gpu/drm/amd/pm/amdgpu_dpm.c

+4 −10
Original line number Diff line number Diff line
@@ -853,22 +853,16 @@ int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, 
				   uint32_t max)

{

	struct smu_context *smu = adev->powerplay.pp_handle;

	int ret = 0;



	if (type != PP_SCLK)

		return -EINVAL;



	if (!is_support_sw_smu(adev))

		return -EOPNOTSUPP;



	mutex_lock(&adev->pm.mutex);

	ret = smu_set_soft_freq_range(smu,

				      SMU_SCLK,

	guard(mutex)(&adev->pm.mutex);



	return smu_set_soft_freq_range(smu,

				      type,

				      min,

				      max);

	mutex_unlock(&adev->pm.mutex);



	return ret;

}



int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev)

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

+13 −1
Original line number Diff line number Diff line
@@ -76,6 +76,7 @@ static void smu_power_profile_mode_get(struct smu_context *smu, 
				       enum PP_SMC_POWER_PROFILE profile_mode);

static void smu_power_profile_mode_put(struct smu_context *smu,

				       enum PP_SMC_POWER_PROFILE profile_mode);

static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type);



static int smu_sys_get_pp_feature_mask(void *handle,

				       char *buf)
@@ -134,12 +135,17 @@ int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 
}



int smu_set_soft_freq_range(struct smu_context *smu,

			    enum smu_clk_type clk_type,

			    enum pp_clock_type type,

			    uint32_t min,

			    uint32_t max)

{

	enum smu_clk_type clk_type;

	int ret = 0;



	clk_type = smu_convert_to_smuclk(type);

	if (clk_type == SMU_CLK_COUNT)

		return -EINVAL;



	if (smu->ppt_funcs->set_soft_freq_limited_range)

		ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,

								  clk_type,
@@ -2980,6 +2986,12 @@ static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 
		clk_type = SMU_DCLK; break;

	case PP_DCLK1:

		clk_type = SMU_DCLK1; break;

	case PP_ISPICLK:

		clk_type = SMU_ISPICLK;

		break;

	case PP_ISPXCLK:

		clk_type = SMU_ISPXCLK;

		break;

	case OD_SCLK:

		clk_type = SMU_OD_SCLK; break;

	case OD_MCLK:

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

+1 −1
Original line number Diff line number Diff line
@@ -1642,7 +1642,7 @@ int smu_write_watermarks_table(struct smu_context *smu); 
int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,

			   uint32_t *min, uint32_t *max);



int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,

int smu_set_soft_freq_range(struct smu_context *smu, enum pp_clock_type clk_type,

			    uint32_t min, uint32_t max);



int smu_set_gfx_power_up_by_imu(struct smu_context *smu);

drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h

+2 −0
Original line number Diff line number Diff line
@@ -305,6 +305,8 @@ enum smu_clk_type { 
	SMU_MCLK,

	SMU_PCIE,

	SMU_LCLK,

	SMU_ISPICLK,

	SMU_ISPXCLK,

	SMU_OD_CCLK,

	SMU_OD_SCLK,

	SMU_OD_MCLK,