Commit 9c2f63da authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Dmitry Baryshkov
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drm/msm/mdp4: register the LVDS PLL as a clock provider



The LVDS/LCDC controller uses pixel clock coming from the multimedia
controller (mmcc) rather than using the PLL directly. Stop using LVDS
PLL directly and register it as a clock provider. Use lcdc_clk as a
pixel clock for the LCDC.

Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/650280/
Link: https://lore.kernel.org/r/20250425-fd-mdp4-lvds-v4-3-6b212160b44c@oss.qualcomm.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
parent f6720d64
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+1 −1
Original line number Diff line number Diff line
@@ -207,6 +207,6 @@ static inline struct drm_encoder *mdp4_dsi_encoder_init(struct drm_device *dev)
}
#endif

struct clk *mpd4_lvds_pll_init(struct drm_device *dev);
struct clk *mpd4_get_lcdc_clock(struct drm_device *dev);

#endif /* __MDP4_KMS_H__ */
+1 −2
Original line number Diff line number Diff line
@@ -380,8 +380,7 @@ struct drm_encoder *mdp4_lcdc_encoder_init(struct drm_device *dev,

	drm_encoder_helper_add(encoder, &mdp4_lcdc_encoder_helper_funcs);

	/* TODO: do we need different pll in other cases? */
	mdp4_lcdc_encoder->lcdc_clk = mpd4_lvds_pll_init(dev);
	mdp4_lcdc_encoder->lcdc_clk = mpd4_get_lcdc_clock(dev);
	if (IS_ERR(mdp4_lcdc_encoder->lcdc_clk)) {
		DRM_DEV_ERROR(dev->dev, "failed to get lvds_clk\n");
		return ERR_CAST(mdp4_lcdc_encoder->lcdc_clk);
+32 −13
Original line number Diff line number Diff line
@@ -133,29 +133,48 @@ static struct clk_init_data pll_init = {
	.num_parents = ARRAY_SIZE(mpd4_lvds_pll_parents),
};

struct clk *mpd4_lvds_pll_init(struct drm_device *dev)
static struct clk_hw *mpd4_lvds_pll_init(struct drm_device *dev)
{
	struct mdp4_lvds_pll *lvds_pll;
	struct clk *clk;
	int ret;

	lvds_pll = devm_kzalloc(dev->dev, sizeof(*lvds_pll), GFP_KERNEL);
	if (!lvds_pll) {
		ret = -ENOMEM;
		goto fail;
	}
	if (!lvds_pll)
		return ERR_PTR(-ENOMEM);

	lvds_pll->dev = dev;

	lvds_pll->pll_hw.init = &pll_init;
	clk = devm_clk_register(dev->dev, &lvds_pll->pll_hw);
	if (IS_ERR(clk)) {
		ret = PTR_ERR(clk);
		goto fail;
	ret = devm_clk_hw_register(dev->dev, &lvds_pll->pll_hw);
	if (ret)
		return ERR_PTR(ret);

	ret = devm_of_clk_add_hw_provider(dev->dev, of_clk_hw_simple_get, &lvds_pll->pll_hw);
	if (ret)
		return ERR_PTR(ret);

	return &lvds_pll->pll_hw;
}

	return clk;
struct clk *mpd4_get_lcdc_clock(struct drm_device *dev)
{
	struct clk_hw *hw;
	struct clk *clk;

fail:
	return ERR_PTR(ret);

	/* TODO: do we need different pll in other cases? */
	hw = mpd4_lvds_pll_init(dev);
	if (IS_ERR(hw)) {
		DRM_DEV_ERROR(dev->dev, "failed to register LVDS PLL\n");
		return ERR_CAST(hw);
	}

	clk = devm_clk_get(dev->dev, "lcdc_clk");
	if (clk == ERR_PTR(-ENOENT)) {
		drm_warn(dev, "can't get LCDC clock, using PLL directly\n");

		return devm_clk_hw_get_clk(dev->dev, hw, "lcdc_clk");
	}

	return clk;
}