Commit 9c2fb0c2 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'samsung-clk-6.14' of... 

Merge tag 'samsung-clk-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung

Pull Samsung clk driver updates from Krzysztof Kozlowski:

 - Add clock controller driver for Exynos990 SoC

* tag 'samsung-clk-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  clk: samsung: Introduce Exynos990 clock controller driver
  clk: samsung: clk-pll: Add support for pll_{0717x, 0718x, 0732x}
  dt-bindings: clock: samsung: Add Exynos990 SoC CMU bindings
parents 40384c84 bdd03ebf

Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml

0 → 100644
+121 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/samsung,exynos990-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Samsung Exynos990 SoC clock controller



maintainers:

  - Igor Belwon <igor.belwon@mentallysanemainliners.org>

  - Chanwoo Choi <cw00.choi@samsung.com>

  - Krzysztof Kozlowski <krzk@kernel.org>



description: |

  Exynos990 clock controller is comprised of several CMU units, generating

  clocks for different domains. Those CMU units are modeled as separate device

  tree nodes, and might depend on each other. The root clock in that root tree

  is an external clock: OSCCLK (26 MHz). This external clock must be defined

  as a fixed-rate clock in dts.



  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and

  dividers; all other clocks of function blocks (other CMUs) are usually

  derived from CMU_TOP.



  Each clock is assigned an identifier and client nodes can use this identifier

  to specify the clock which they consume. All clocks available for usage

  in clock consumer nodes are defined as preprocessor macros in

  'include/dt-bindings/clock/samsung,exynos990.h' header.



properties:

  compatible:

    enum:

      - samsung,exynos990-cmu-hsi0

      - samsung,exynos990-cmu-top



  clocks:

    minItems: 1

    maxItems: 5



  clock-names:

    minItems: 1

    maxItems: 5



  "#clock-cells":

    const: 1



  reg:

    maxItems: 1



required:

  - compatible

  - clocks

  - clock-names

  - "#clock-cells"

  - reg



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos990-cmu-hsi0



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: CMU_HSI0 BUS clock (from CMU_TOP)

            - description: CMU_HSI0 USB31DRD clock (from CMU_TOP)

            - description: CMU_HSI0 USBDP_DEBUG clock (from CMU_TOP)

            - description: CMU_HSI0 DPGTC clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: bus

            - const: usb31drd

            - const: usbdp_debug

            - const: dpgtc



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos990-cmu-top



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)



        clock-names:

          items:

            - const: oscclk



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/samsung,exynos990.h>



    cmu_hsi0: clock-controller@10a00000 {

        compatible = "samsung,exynos990-cmu-hsi0";

        reg = <0x10a00000 0x8000>;

        #clock-cells = <1>;



        clocks = <&oscclk>,

                 <&cmu_top CLK_DOUT_CMU_HSI0_BUS>,

                 <&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>,

                 <&cmu_top CLK_DOUT_CMU_HSI0_USBDP_DEBUG>,

                 <&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>;

        clock-names = "oscclk",

                      "bus",

                      "usb31drd",

                      "usbdp_debug",

                      "dpgtc";

    };



...

drivers/clk/samsung/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o 
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos7885.o

obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos850.o

obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos8895.o

obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos990.o

obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynosautov9.o

obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynosautov920.o

obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-gs101.o

drivers/clk/samsung/clk-exynos990.c

0 → 100644
+1343 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/clk/samsung/clk-pll.c

+12 −2
Original line number Diff line number Diff line
@@ -430,7 +430,10 @@ static const struct clk_ops samsung_pll36xx_clk_min_ops = { 
#define PLL0822X_LOCK_STAT_SHIFT	(29)

#define PLL0822X_ENABLE_SHIFT		(31)



/* PLL1418x is similar to PLL0822x, except that MDIV is one bit smaller */

/*

 * PLL1418x, PLL0717x and PLL0718x are similar

 * to PLL0822x, except that MDIV is one bit smaller

 */

#define PLL1418X_MDIV_MASK		(0x1FF)



static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
@@ -441,10 +444,14 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw, 
	u64 fvco = parent_rate;



	pll_con3 = readl_relaxed(pll->con_reg);

	if (pll->type != pll_1418x)



	if (pll->type != pll_1418x &&

	    pll->type != pll_0717x &&

	    pll->type != pll_0718x)

		mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK;

	else

		mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL1418X_MDIV_MASK;



	pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;

	sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
@@ -1377,6 +1384,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, 
	case pll_0516x:

	case pll_0517x:

	case pll_0518x:

	case pll_0717x:

	case pll_0718x:

	case pll_0732x:

		pll->enable_offs = PLL0822X_ENABLE_SHIFT;

		pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;

		if (!pll->rate_table)

drivers/clk/samsung/clk-pll.h

+3 −0
Original line number Diff line number Diff line
@@ -45,6 +45,9 @@ enum samsung_pll_type { 
	pll_531x,

	pll_1051x,

	pll_1052x,

	pll_0717x,

	pll_0718x,

	pll_0732x,

};



#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \