Unverified Commit 9c433c87 authored by Marek Vasut's avatar Marek Vasut Committed by Robert Foss
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drm/bridge: tc358767: Set LSCLK divider for SYSCLK to 1 



The only information in the datasheet regarding this divider is a note
in SYS_PLLPARAM register documentation which states that when LSCLK is
270 MHz, LSCLK_DIV should be 1. What should LSCLK_DIV be set to when
LSCLK is 162 MHz (for DP 1.62G mode) is unclear, but empirical test
confirms using LSCLK_DIV 1 has no adverse effects either. In the worst
case, the internal TC358767 clock would run faster.

Reviewed-by: default avatarAlexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Signed-off-by: default avatarRobert Foss <rfoss@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240625120334.145320-4-marex@denx.de
parent 3f13e53b

drivers/gpu/drm/bridge/tc358767.c

+1 −1
Original line number Diff line number Diff line
@@ -738,7 +738,7 @@ static int tc_stream_clock_calc(struct tc_data *tc) 
static int tc_set_syspllparam(struct tc_data *tc)

{

	unsigned long rate;

	u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2;

	u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_1;



	rate = clk_get_rate(tc->refclk);

	switch (rate) {