Commit 9c749e61 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arc-6.7-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc 

Pull ARC fixes from Vineet Gupta:

 - build error for hugetlb, sparse and smatch fixes

 - removal of VIPT aliasing cache code

* tag 'arc-6.7-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
  ARC: add hugetlb definitions
  ARC: fix smatch warning
  ARC: fix spare error
  ARC: mm: retire support for aliasing VIPT D$
  ARC: entry: move ARCompact specific bits out of entry.h
  ARC: entry: SAVE_ABI_CALLEE_REG: ISA/ABI specific helper
parents 3f10e214 9a733dc4

arch/arc/Kconfig

+0 −5
Original line number Diff line number Diff line
@@ -49,7 +49,6 @@ config ARC 
	select OF

	select OF_EARLY_FLATTREE

	select PCI_SYSCALL if PCI

	select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING

	select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32

	select TRACE_IRQFLAGS_SUPPORT
@@ -232,10 +231,6 @@ config ARC_CACHE_PAGES 
	  Note that Global I/D ENABLE + Per Page DISABLE works but corollary

	  Global DISABLE + Per Page ENABLE won't work



config ARC_CACHE_VIPT_ALIASING

	bool "Support VIPT Aliasing D$"

	depends on ARC_HAS_DCACHE && ISA_ARCOMPACT



endif #ARC_CACHE



config ARC_HAS_ICCM

arch/arc/include/asm/cacheflush.h

+0 −43
Original line number Diff line number Diff line
@@ -44,31 +44,10 @@ void dma_cache_wback(phys_addr_t start, unsigned long sz); 


#define flush_cache_dup_mm(mm)			/* called on fork (VIVT only) */



#ifndef CONFIG_ARC_CACHE_VIPT_ALIASING



#define flush_cache_mm(mm)			/* called on munmap/exit */

#define flush_cache_range(mm, u_vstart, u_vend)

#define flush_cache_page(vma, u_vaddr, pfn)	/* PF handling/COW-break */



#else	/* VIPT aliasing dcache */



/* To clear out stale userspace mappings */

void flush_cache_mm(struct mm_struct *mm);

void flush_cache_range(struct vm_area_struct *vma,

	unsigned long start,unsigned long end);

void flush_cache_page(struct vm_area_struct *vma,

	unsigned long user_addr, unsigned long page);



/*

 * To make sure that userspace mapping is flushed to memory before

 * get_user_pages() uses a kernel mapping to access the page

 */

#define ARCH_HAS_FLUSH_ANON_PAGE

void flush_anon_page(struct vm_area_struct *vma,

	struct page *page, unsigned long u_vaddr);



#endif	/* CONFIG_ARC_CACHE_VIPT_ALIASING */



/*

 * A new pagecache page has PG_arch_1 clear - thus dcache dirty by default

 * This works around some PIO based drivers which don't call flush_dcache_page
@@ -76,28 +55,6 @@ void flush_anon_page(struct vm_area_struct *vma, 
 */

#define PG_dc_clean	PG_arch_1



#define CACHE_COLORS_NUM	4

#define CACHE_COLORS_MSK	(CACHE_COLORS_NUM - 1)

#define CACHE_COLOR(addr)	(((unsigned long)(addr) >> (PAGE_SHIFT)) & CACHE_COLORS_MSK)



/*

 * Simple wrapper over config option

 * Bootup code ensures that hardware matches kernel configuration

 */

static inline int cache_is_vipt_aliasing(void)

{

	return IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING);

}



/*

 * checks if two addresses (after page aligning) index into same cache set

 */

#define addr_not_cache_congruent(addr1, addr2)				\

({									\

	cache_is_vipt_aliasing() ? 					\

		(CACHE_COLOR(addr1) != CACHE_COLOR(addr2)) : 0;		\

})



#define copy_to_user_page(vma, page, vaddr, dst, src, len)		\

do {									\

	memcpy(dst, src, len);						\

arch/arc/include/asm/entry-arcv2.h

+32 −0
Original line number Diff line number Diff line
@@ -291,4 +291,36 @@ 
				/* M = 8-1  N = 8 */

.endm



.macro SAVE_ABI_CALLEE_REGS

	push	r13

	push	r14

	push	r15

	push	r16

	push	r17

	push	r18

	push	r19

	push	r20

	push	r21

	push	r22

	push	r23

	push	r24

	push	r25

.endm



.macro RESTORE_ABI_CALLEE_REGS

	pop	r25

	pop	r24

	pop	r23

	pop	r22

	pop	r21

	pop	r20

	pop	r19

	pop	r18

	pop	r17

	pop	r16

	pop	r15

	pop	r14

	pop	r13

.endm



#endif

arch/arc/include/asm/entry-compact.h

+86 −1
Original line number Diff line number Diff line
@@ -33,6 +33,91 @@ 
#include <asm/irqflags-compact.h>

#include <asm/thread_info.h>	/* For THREAD_SIZE */



/* Note on the LD/ST addr modes with addr reg wback

 *

 * LD.a same as LD.aw

 *

 * LD.a    reg1, [reg2, x]  => Pre Incr

 *      Eff Addr for load = [reg2 + x]

 *

 * LD.ab   reg1, [reg2, x]  => Post Incr

 *      Eff Addr for load = [reg2]

 */



.macro PUSHAX aux

	lr	r9, [\aux]

	push	r9

.endm



.macro POPAX aux

	pop	r9

	sr	r9, [\aux]

.endm



.macro  SAVE_R0_TO_R12

	push	r0

	push	r1

	push	r2

	push	r3

	push	r4

	push	r5

	push	r6

	push	r7

	push	r8

	push	r9

	push	r10

	push	r11

	push	r12

.endm



.macro RESTORE_R12_TO_R0

	pop	r12

	pop	r11

	pop	r10

	pop	r9

	pop	r8

	pop	r7

	pop	r6

	pop	r5

	pop	r4

	pop	r3

	pop	r2

	pop	r1

	pop	r0

.endm



.macro SAVE_ABI_CALLEE_REGS

	push	r13

	push	r14

	push	r15

	push	r16

	push	r17

	push	r18

	push	r19

	push	r20

	push	r21

	push	r22

	push	r23

	push	r24

	push	r25

.endm



.macro RESTORE_ABI_CALLEE_REGS

	pop	r25

	pop	r24

	pop	r23

	pop	r22

	pop	r21

	pop	r20

	pop	r19

	pop	r18

	pop	r17

	pop	r16

	pop	r15

	pop	r14

	pop	r13

.endm



/*--------------------------------------------------------------

 * Switch to Kernel Mode stack if SP points to User Mode stack

 *
@@ -235,7 +320,7 @@ 
	SWITCH_TO_KERNEL_STK





	PUSH	0x003\LVL\()abcd    /* Dummy ECR */

	st.a	0x003\LVL\()abcd, [sp, -4]	/* Dummy ECR */

	sub	sp, sp, 8	    /* skip orig_r0 (not needed)

				       skip pt_regs->sp, already saved above */

arch/arc/include/asm/entry.h

+4 −106
Original line number Diff line number Diff line
@@ -21,114 +21,12 @@ 
#include <asm/entry-arcv2.h>

#endif



/* Note on the LD/ST addr modes with addr reg wback

 *

 * LD.a same as LD.aw

 *

 * LD.a    reg1, [reg2, x]  => Pre Incr

 *      Eff Addr for load = [reg2 + x]

 *

 * LD.ab   reg1, [reg2, x]  => Post Incr

 *      Eff Addr for load = [reg2]

 */



.macro PUSH reg

	st.a	\reg, [sp, -4]

.endm



.macro PUSHAX aux

	lr	r9, [\aux]

	PUSH	r9

.endm



.macro POP reg

	ld.ab	\reg, [sp, 4]

.endm



.macro POPAX aux

	POP	r9

	sr	r9, [\aux]

.endm



/*--------------------------------------------------------------

 * Helpers to save/restore Scratch Regs:

 * used by Interrupt/Exception Prologue/Epilogue

 *-------------------------------------------------------------*/

.macro  SAVE_R0_TO_R12

	PUSH	r0

	PUSH	r1

	PUSH	r2

	PUSH	r3

	PUSH	r4

	PUSH	r5

	PUSH	r6

	PUSH	r7

	PUSH	r8

	PUSH	r9

	PUSH	r10

	PUSH	r11

	PUSH	r12

.endm



.macro RESTORE_R12_TO_R0

	POP	r12

	POP	r11

	POP	r10

	POP	r9

	POP	r8

	POP	r7

	POP	r6

	POP	r5

	POP	r4

	POP	r3

	POP	r2

	POP	r1

	POP	r0



.endm



/*--------------------------------------------------------------

 * Helpers to save/restore callee-saved regs:

 * used by several macros below

 *-------------------------------------------------------------*/

.macro SAVE_R13_TO_R25

	PUSH	r13

	PUSH	r14

	PUSH	r15

	PUSH	r16

	PUSH	r17

	PUSH	r18

	PUSH	r19

	PUSH	r20

	PUSH	r21

	PUSH	r22

	PUSH	r23

	PUSH	r24

	PUSH	r25

.endm



.macro RESTORE_R25_TO_R13

	POP	r25

	POP	r24

	POP	r23

	POP	r22

	POP	r21

	POP	r20

	POP	r19

	POP	r18

	POP	r17

	POP	r16

	POP	r15

	POP	r14

	POP	r13

.endm



/*

 * save user mode callee regs as struct callee_regs

 *  - needed by fork/do_signal/unaligned-access-emulation.

 */

.macro SAVE_CALLEE_SAVED_USER

	SAVE_R13_TO_R25

	SAVE_ABI_CALLEE_REGS

.endm



/*
@@ -136,18 +34,18 @@ 
 *  - could have been changed by ptrace tracer or unaligned-access fixup

 */

.macro RESTORE_CALLEE_SAVED_USER

	RESTORE_R25_TO_R13

	RESTORE_ABI_CALLEE_REGS

.endm



/*

 * save/restore kernel mode callee regs at the time of context switch

 */

.macro SAVE_CALLEE_SAVED_KERNEL

	SAVE_R13_TO_R25

	SAVE_ABI_CALLEE_REGS

.endm



.macro RESTORE_CALLEE_SAVED_KERNEL

	RESTORE_R25_TO_R13

	RESTORE_ABI_CALLEE_REGS

.endm



/*--------------------------------------------------------------