Commit 9cc06dba authored by Simona Vetter's avatar Simona Vetter
Browse files

Merge tag 'drm-intel-next-2024-12-11' of... 

Merge tag 'drm-intel-next-2024-12-11' of https://gitlab.freedesktop.org/drm/i915/kernel

 into drm-next

Core Changes:
 - drm/print: add drm_print_hex_dump()

Driver Changes:
 - HDCP fixes and updates for Xe3lpd and for HDCP 1.4 (Suraj)
 - Add dedicated lock for each sideband (Jani)
 - New GSC FW for ARL-H and ARL-U (Daniele)
 - Add support for 3 VDSC engines 12 slices (Ankit)
 - Sanitize MBUS joining (Ville)
 - Fixes in DP MST (Imre)
 - Stop using pixel_format_from_register_bits() to parse VBT (Ville)
 - Declutter CDCLK code (Ville)
 - PSR clean up and fixes (Jouni, Jani, Animesh)
 - DMC wakelock - Fixes and enablement for Xe3_LPD (Gustavo)
 - Demote source OUI read/write failure logging to debug (Jani)
 - Potential boot oops fix and some general cleanups (Ville)
 - Scaler code cleanups (Ville)
 - More conversion towards struct intel_display and general cleanups (Jani)
 - Limit max compressed bpp to 18 when forcing DSC (Ankit)
 - Start to reconcile i915's and xe's display power mgt sequences (Rodrigo)
 - Some correction in the DP Link Training sequence (Arun)
 - Avoid setting YUV420_MODE in PIPE_MISC on Xe3lpd (Ankit)
 - MST and DDI cleanups and refactoring (Jani)
 - Fixed an typo in i915_gem_gtt.c (Zhang)
 - Try to make DPT shrinkable again (Ville)
 - Try to fix CPU MMIO fails during legacy LUT updates (Ville)
 - Some PPS cleanups (Ville, Jani)
 - Use seq buf for printing rates (Jani)
 - Flush DMC wakelock release work at the end of runtime suspend (Gustavo)
 - Fix NULL pointer dereference in capture_engine (Eugene)
 - Fix memory leak by correcting cache object name in error handler (Jiasheng)
 - Small refactor in WM/DPKGC for modifying latency programmed into PKG_C_LATENCY (Suraj)
 - Add drm_printer based hex dumper and use it (Jani)
 - Move g4x code to specific g4x functions (Jani)

Signed-off-by: default avatarSimona Vetter <simona.vetter@ffwll.ch>
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
[sima: conflict in intel_dp_mst.c due to conversion to
drm_connector_dynamic_init that landed through drm-misc]
Link: https://patchwork.freedesktop.org/patch/msgid/Z1n4VhatZpvT5xKs@intel.com
parents d678c635 e7f0a3a6

drivers/gpu/drm/drm_print.c

+23 −0
Original line number Diff line number Diff line
@@ -390,3 +390,26 @@ void drm_print_regset32(struct drm_printer *p, struct debugfs_regset32 *regset) 
	}

}

EXPORT_SYMBOL(drm_print_regset32);



/**

 * drm_print_hex_dump - print a hex dump to a &drm_printer stream

 * @p: The &drm_printer

 * @prefix: Prefix for each line, may be NULL for no prefix

 * @buf: Buffer to dump

 * @len: Length of buffer

 *

 * Print hex dump to &drm_printer, with 16 space-separated hex bytes per line,

 * optionally with a prefix on each line. No separator is added after prefix.

 */

void drm_print_hex_dump(struct drm_printer *p, const char *prefix,

			const u8 *buf, size_t len)

{

	int i;



	for (i = 0; i < len; i += 16) {

		int bytes_per_line = min(16, len - i);



		drm_printf(p, "%s%*ph\n", prefix ?: "", bytes_per_line, buf + i);

	}

}

EXPORT_SYMBOL(drm_print_hex_dump);

drivers/gpu/drm/i915/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -30,7 +30,6 @@ i915-y += \ 
	i915_params.o \

	i915_pci.o \

	i915_scatterlist.o \

	i915_suspend.o \

	i915_switcheroo.o \

	i915_sysfs.o \

	i915_utils.o \
@@ -220,6 +219,7 @@ i915-$(CONFIG_HWMON) += \ 
i915-y += \

	display/hsw_ips.o \

	display/i9xx_plane.o \

	display/i9xx_display_sr.o \

	display/i9xx_wm.o \

	display/intel_alpm.o \

	display/intel_atomic.o \

drivers/gpu/drm/i915/display/g4x_dp.c

+22 −3
Original line number Diff line number Diff line
@@ -55,7 +55,7 @@ const struct dpll *vlv_get_dpll(struct drm_i915_private *i915) 
	return IS_CHERRYVIEW(i915) ? &chv_dpll[0] : &vlv_dpll[0];

}



void g4x_dp_set_clock(struct intel_encoder *encoder,

static void g4x_dp_set_clock(struct intel_encoder *encoder,

			     struct intel_crtc_state *pipe_config)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -1223,6 +1223,25 @@ static bool ilk_digital_port_connected(struct intel_encoder *encoder) 
	return intel_de_read(display, DEISR) & bit;

}



static int g4x_dp_compute_config(struct intel_encoder *encoder,

				 struct intel_crtc_state *crtc_state,

				 struct drm_connector_state *conn_state)

{

	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	int ret;



	if (HAS_PCH_SPLIT(i915) && encoder->port != PORT_A)

		crtc_state->has_pch_encoder = true;



	ret = intel_dp_compute_config(encoder, crtc_state, conn_state);

	if (ret)

		return ret;



	g4x_dp_set_clock(encoder, crtc_state);



	return 0;

}



static void g4x_dp_suspend_complete(struct intel_encoder *encoder)

{

	/*
@@ -1307,7 +1326,7 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv, 
	intel_encoder_link_check_init(intel_encoder, intel_dp_link_check);



	intel_encoder->hotplug = intel_dp_hotplug;

	intel_encoder->compute_config = intel_dp_compute_config;

	intel_encoder->compute_config = g4x_dp_compute_config;

	intel_encoder->get_hw_state = intel_dp_get_hw_state;

	intel_encoder->get_config = intel_dp_get_config;

	intel_encoder->sync_state = intel_dp_sync_state;

drivers/gpu/drm/i915/display/g4x_dp.h

+0 −6
Original line number Diff line number Diff line
@@ -19,8 +19,6 @@ struct intel_encoder; 


#ifdef I915

const struct dpll *vlv_get_dpll(struct drm_i915_private *i915);

void g4x_dp_set_clock(struct intel_encoder *encoder,

		      struct intel_crtc_state *pipe_config);

bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,

			 i915_reg_t dp_reg, enum port port,

			 enum pipe *pipe);
@@ -31,10 +29,6 @@ static inline const struct dpll *vlv_get_dpll(struct drm_i915_private *i915) 
{

	return NULL;

}

static inline void g4x_dp_set_clock(struct intel_encoder *encoder,

				    struct intel_crtc_state *pipe_config)

{

}

static inline bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,

				       i915_reg_t dp_reg, int port,

				       enum pipe *pipe)

drivers/gpu/drm/i915/display/hsw_ips.c

+18 −2
Original line number Diff line number Diff line
@@ -185,10 +185,12 @@ void hsw_ips_post_update(struct intel_atomic_state *state, 
/* IPS only exists on ULT machines and is tied to pipe A. */

bool hsw_crtc_supports_ips(struct intel_crtc *crtc)

{

	return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;

	struct intel_display *display = to_intel_display(crtc);



	return HAS_IPS(display) && crtc->pipe == PIPE_A;

}



bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)

static bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(crtc_state);

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -218,6 +220,20 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state) 
	return true;

}



int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);



	if (!IS_BROADWELL(i915))

		return 0;



	if (!hsw_crtc_state_ips_capable(crtc_state))

		return 0;



	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */

	return DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95);

}



int hsw_ips_compute_config(struct intel_atomic_state *state,

			   struct intel_crtc *crtc)

{