Commit 9d10cd52 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2026-01-15' of... 

Merge tag 'drm-intel-next-2026-01-15' of https://gitlab.freedesktop.org/drm/i915/kernel

 into drm-next

Beyond Display:
 - Make 'guc_hw_reg_state' static as it isn't exported (Ben)
 - Fix doc build on mei related interface header (Jani)

Display related:
 - Fix ggtt fb alignment on Xe display (Tvrtko)
 - More display clean-up towards deduplication and full separation (Jani)
 - Use the consolidated HDMI tables (Suraj)
 - Account for DSC slice overhead (Ankit)
 - Prepare GVT for display modularization (Ankit, Jani)
 - Enable/Disable DC balance along with VRR DSB (Mitul, Ville)
 - Protection against unsupported modes in LT PHY (Suraj)
 - Display W/a addition and fixes (Gustavo)
 - Fix many SPDX identifier comments (Ankit)
 - Incorporate Xe3_LPD changes for CD2X divider (Gustavo)
 - Clean up link BW/DSC slice config computation (Imre)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patch.msgid.link/aWkNThVRSkGAfUVv@intel.com
parents 37b812b7 d30f75d2

drivers/gpu/drm/i915/Makefile

+5 −1
Original line number Diff line number Diff line
@@ -78,6 +78,7 @@ i915-$(CONFIG_PERF_EVENTS) += \ 
i915-y += \

	i915_display_pc8.o \

	i915_hdcp_gsc.o \

	i915_initial_plane.o \

	i915_panic.o



# "Graphics Technology" (aka we talk to the gpu)
@@ -288,6 +289,7 @@ i915-y += \ 
	display/intel_hotplug.o \

	display/intel_hotplug_irq.o \

	display/intel_hti.o \

	display/intel_initial_plane.o \

	display/intel_link_bw.o \

	display/intel_load_detect.o \

	display/intel_lpe_audio.o \
@@ -300,7 +302,6 @@ i915-y += \ 
	display/intel_pch_display.o \

	display/intel_pch_refclk.o \

	display/intel_plane.o \

	display/intel_plane_initial.o \

	display/intel_pmdemand.o \

	display/intel_psr.o \

	display/intel_quirks.o \
@@ -381,6 +382,9 @@ i915-y += \ 
i915-$(CONFIG_DRM_I915_DP_TUNNEL) += \

	display/intel_dp_tunnel.o



i915-$(CONFIG_DRM_I915_GVT) += \

	display/intel_gvt_api.o



i915-y += \

	i915_perf.o

drivers/gpu/drm/i915/display/i9xx_wm.c

+8 −9
Original line number Diff line number Diff line
@@ -7,7 +7,6 @@ 


#include <drm/drm_print.h>



#include "i915_drv.h"

#include "i915_reg.h"

#include "i9xx_wm.h"

#include "i9xx_wm_regs.h"
@@ -17,6 +16,7 @@ 
#include "intel_display.h"

#include "intel_display_regs.h"

#include "intel_display_trace.h"

#include "intel_display_utils.h"

#include "intel_dram.h"

#include "intel_fb.h"

#include "intel_mchbar_regs.h"
@@ -1863,8 +1863,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state, 
				   struct intel_crtc *crtc)

{

	struct intel_display *display = to_intel_display(crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	struct intel_uncore *uncore = &dev_priv->uncore;

	struct intel_uncore *uncore = to_intel_uncore(display->drm);

	const struct intel_crtc_state *crtc_state =

		intel_atomic_get_new_crtc_state(state, crtc);

	const struct vlv_fifo_state *fifo_state =
@@ -2743,12 +2742,12 @@ static void ilk_compute_wm_level(struct intel_display *display, 


static void hsw_read_wm_latency(struct intel_display *display, u16 wm[])

{

	struct drm_i915_private *i915 = to_i915(display->drm);

	struct intel_uncore *uncore = to_intel_uncore(display->drm);

	u64 sskpd;



	display->wm.num_levels = 5;



	sskpd = intel_uncore_read64(&i915->uncore, MCH_SSKPD);

	sskpd = intel_uncore_read64(uncore, MCH_SSKPD);



	wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);

	if (wm[0] == 0)
@@ -2761,12 +2760,12 @@ static void hsw_read_wm_latency(struct intel_display *display, u16 wm[]) 


static void snb_read_wm_latency(struct intel_display *display, u16 wm[])

{

	struct drm_i915_private *i915 = to_i915(display->drm);

	struct intel_uncore *uncore = to_intel_uncore(display->drm);

	u32 sskpd;



	display->wm.num_levels = 4;



	sskpd = intel_uncore_read(&i915->uncore, MCH_SSKPD);

	sskpd = intel_uncore_read(uncore, MCH_SSKPD);



	wm[0] = REG_FIELD_GET(SSKPD_WM0_MASK_SNB, sskpd);

	wm[1] = REG_FIELD_GET(SSKPD_WM1_MASK_SNB, sskpd);
@@ -2776,12 +2775,12 @@ static void snb_read_wm_latency(struct intel_display *display, u16 wm[]) 


static void ilk_read_wm_latency(struct intel_display *display, u16 wm[])

{

	struct drm_i915_private *i915 = to_i915(display->drm);

	struct intel_uncore *uncore = to_intel_uncore(display->drm);

	u32 mltr;



	display->wm.num_levels = 3;



	mltr = intel_uncore_read(&i915->uncore, MLTR_ILK);

	mltr = intel_uncore_read(uncore, MLTR_ILK);



	/* ILK primary LP0 latency is 700 ns */

	wm[0] = 7;

drivers/gpu/drm/i915/display/intel_alpm.h

+2 −2
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: MIT

 *

/* SPDX-License-Identifier: MIT */

/*

 * Copyright © 2024 Intel Corporation

 */

drivers/gpu/drm/i915/display/intel_bw.c

+8 −11
Original line number Diff line number Diff line
@@ -6,7 +6,6 @@ 
#include <drm/drm_atomic_state_helper.h>

#include <drm/drm_print.h>



#include "i915_drv.h"

#include "i915_reg.h"

#include "intel_bw.h"

#include "intel_crtc.h"
@@ -75,11 +74,11 @@ static int dg1_mchbar_read_qgv_point_info(struct intel_display *display, 
					  struct intel_qgv_point *sp,

					  int point)

{

	struct drm_i915_private *i915 = to_i915(display->drm);

	struct intel_uncore *uncore = to_intel_uncore(display->drm);

	u32 dclk_ratio, dclk_reference;

	u32 val;



	val = intel_uncore_read(&i915->uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC);

	val = intel_uncore_read(uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC);

	dclk_ratio = REG_FIELD_GET(DG1_QCLK_RATIO_MASK, val);

	if (val & DG1_QCLK_REFERENCE)

		dclk_reference = 6; /* 6 * 16.666 MHz = 100 MHz */
@@ -87,18 +86,18 @@ static int dg1_mchbar_read_qgv_point_info(struct intel_display *display, 
		dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */

	sp->dclk = DIV_ROUND_UP((16667 * dclk_ratio * dclk_reference) + 500, 1000);



	val = intel_uncore_read(&i915->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);

	val = intel_uncore_read(uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);

	if (val & DG1_GEAR_TYPE)

		sp->dclk *= 2;



	if (sp->dclk == 0)

		return -EINVAL;



	val = intel_uncore_read(&i915->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);

	val = intel_uncore_read(uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);

	sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val);

	sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val);



	val = intel_uncore_read(&i915->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH);

	val = intel_uncore_read(uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH);

	sp->t_rcd = REG_FIELD_GET(DG1_DRAM_T_RCD_MASK, val);

	sp->t_ras = REG_FIELD_GET(DG1_DRAM_T_RAS_MASK, val);
@@ -212,14 +211,12 @@ static int icl_pcode_restrict_qgv_points(struct intel_display *display, 
static int mtl_read_qgv_point_info(struct intel_display *display,

				   struct intel_qgv_point *sp, int point)

{

	struct drm_i915_private *i915 = to_i915(display->drm);

	struct intel_uncore *uncore = to_intel_uncore(display->drm);

	u32 val, val2;

	u16 dclk;



	val = intel_uncore_read(&i915->uncore,

				MTL_MEM_SS_INFO_QGV_POINT_LOW(point));

	val2 = intel_uncore_read(&i915->uncore,

				 MTL_MEM_SS_INFO_QGV_POINT_HIGH(point));

	val = intel_uncore_read(uncore, MTL_MEM_SS_INFO_QGV_POINT_LOW(point));

	val2 = intel_uncore_read(uncore, MTL_MEM_SS_INFO_QGV_POINT_HIGH(point));

	dclk = REG_FIELD_GET(MTL_DCLK_MASK, val);

	sp->dclk = DIV_ROUND_CLOSEST(16667 * dclk, 1000);

	sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val);

drivers/gpu/drm/i915/display/intel_cdclk.c

+51 −9
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ 
#include "intel_display_regs.h"

#include "intel_display_types.h"

#include "intel_display_utils.h"

#include "intel_display_wa.h"

#include "intel_dram.h"

#include "intel_mchbar_regs.h"

#include "intel_pci_config.h"
@@ -1858,6 +1859,20 @@ static void bxt_de_pll_enable(struct intel_display *display, int vco) 


static void icl_cdclk_pll_disable(struct intel_display *display)

{

	/*

	 * Wa_13012396614:

	 * Fixes: A sporadic race condition between MDCLK selection and PLL

	 *        enabling.

	 * Workaround:

	 *   Change programming of MDCLK source selection in CDCLK_CTL:

	 *    - When disabling the CDCLK PLL, first set MDCLK source to be CD2XCLK.

	 *    - When enabling the CDCLK PLL, update MDCLK source selection only

	 *      after the PLL is enabled (which is already done as part of the

	 *      normal flow of _bxt_set_cdclk()).

	 */

	if (intel_display_wa(display, 13012396614))

		intel_de_rmw(display, CDCLK_CTL, MDCLK_SOURCE_SEL_MASK, MDCLK_SOURCE_SEL_CD2XCLK);



	intel_de_rmw(display, BXT_DE_PLL_ENABLE,

		     BXT_DE_PLL_PLL_ENABLE, 0);
@@ -1933,6 +1948,8 @@ static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe) 
static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display,

				  int cdclk, int vco, u16 waveform)

{

	u32 ret;



	/* cdclk = vco / 2 / div{1,1.5,2,4} */

	switch (cdclk_divider(cdclk, vco, waveform)) {

	default:
@@ -1941,14 +1958,27 @@ static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display, 
		drm_WARN_ON(display->drm, vco != 0);

		fallthrough;

	case 2:

		return BXT_CDCLK_CD2X_DIV_SEL_1;

		ret = BXT_CDCLK_CD2X_DIV_SEL_1;

		break;

	case 3:

		return BXT_CDCLK_CD2X_DIV_SEL_1_5;

		ret = BXT_CDCLK_CD2X_DIV_SEL_1_5;

		break;

	case 4:

		return BXT_CDCLK_CD2X_DIV_SEL_2;

		ret = BXT_CDCLK_CD2X_DIV_SEL_2;

		break;

	case 8:

		return BXT_CDCLK_CD2X_DIV_SEL_4;

		ret = BXT_CDCLK_CD2X_DIV_SEL_4;

		break;

	}



	/*

	 * On Xe3_LPD onward, the expectation is to always have

	 * BXT_CDCLK_CD2X_DIV_SEL_1 as the default.

	 */

	if (DISPLAY_VER(display) >= 30)

		drm_WARN_ON(display->drm, ret != BXT_CDCLK_CD2X_DIV_SEL_1);



	return ret;

}



static u16 cdclk_squash_waveform(struct intel_display *display,
@@ -2136,8 +2166,10 @@ static u32 bxt_cdclk_ctl(struct intel_display *display, 


	waveform = cdclk_squash_waveform(display, cdclk);



	val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) |

		bxt_cdclk_cd2x_pipe(display, pipe);

	val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform);



	if (DISPLAY_VER(display) < 30)

		val |= bxt_cdclk_cd2x_pipe(display, pipe);



	/*

	 * Disable SSA Precharge when CD clock frequency < 500 MHz,
@@ -2147,10 +2179,20 @@ static u32 bxt_cdclk_ctl(struct intel_display *display, 
	    cdclk >= 500000)

		val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;



	if (DISPLAY_VER(display) >= 20)

		val |= xe2lpd_mdclk_source_sel(display);

	if (DISPLAY_VER(display) >= 20) {

		/*

		 * Wa_13012396614 requires selecting CD2XCLK as MDCLK source

		 * prior to disabling the PLL, which is already handled by

		 * icl_cdclk_pll_disable().  Here we are just making sure

		 * we keep the expected value.

		 */

		if (intel_display_wa(display, 13012396614) && vco == 0)

			val |= MDCLK_SOURCE_SEL_CD2XCLK;

		else

			val |= xe2lpd_mdclk_source_sel(display);

	} else {

		val |= skl_cdclk_decimal(cdclk);

	}



	return val;

}