Commit 9d451912 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86_urgent_for_v6.8_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 fixes from Borislav Petkov:

 - Make sure 32-bit syscall registers are properly sign-extended

 - Add detection for AMD's Zen5 generation CPUs and Intel's Clearwater
   Forest CPU model number

 - Make a stub function export non-GPL because it is part of the
   paravirt alternatives and that can be used by non-GPL code

* tag 'x86_urgent_for_v6.8_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/CPU/AMD: Add more models to X86_FEATURE_ZEN5
  x86/entry/ia32: Ensure s32 is sign extended to s64
  x86/cpu: Add model number for Intel Clearwater Forest processor
  x86/CPU/AMD: Add X86_FEATURE_ZEN5
  x86/paravirt: Make BUG_func() usable by non-GPL modules
parents a08ebda9 b9328fd6

arch/x86/include/asm/cpufeatures.h

+1 −3
Original line number Diff line number Diff line
@@ -81,10 +81,8 @@ 
#define X86_FEATURE_K6_MTRR		( 3*32+ 1) /* AMD K6 nonstandard MTRRs */

#define X86_FEATURE_CYRIX_ARR		( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */

#define X86_FEATURE_CENTAUR_MCR		( 3*32+ 3) /* Centaur MCRs (= MTRRs) */



/* CPU types for specific tunings: */

#define X86_FEATURE_K8			( 3*32+ 4) /* "" Opteron, Athlon64 */

/* FREE, was #define X86_FEATURE_K7			( 3*32+ 5) "" Athlon */

#define X86_FEATURE_ZEN5		( 3*32+ 5) /* "" CPU based on Zen5 microarchitecture */

#define X86_FEATURE_P3			( 3*32+ 6) /* "" P3 */

#define X86_FEATURE_P4			( 3*32+ 7) /* "" P4 */

#define X86_FEATURE_CONSTANT_TSC	( 3*32+ 8) /* TSC ticks at a constant rate */

arch/x86/include/asm/intel-family.h

+2 −0
Original line number Diff line number Diff line
@@ -162,6 +162,8 @@ 
#define INTEL_FAM6_ATOM_CRESTMONT_X	0xAF /* Sierra Forest */

#define INTEL_FAM6_ATOM_CRESTMONT	0xB6 /* Grand Ridge */



#define INTEL_FAM6_ATOM_DARKMONT_X	0xDD /* Clearwater Forest */



/* Xeon Phi */



#define INTEL_FAM6_XEON_PHI_KNL		0x57 /* Knights Landing */

arch/x86/include/asm/syscall_wrapper.h

+21 −4
Original line number Diff line number Diff line
@@ -58,12 +58,29 @@ extern long __ia32_sys_ni_syscall(const struct pt_regs *regs); 
		,,regs->di,,regs->si,,regs->dx				\

		,,regs->r10,,regs->r8,,regs->r9)			\





/* SYSCALL_PT_ARGS is Adapted from s390x */

#define SYSCALL_PT_ARG6(m, t1, t2, t3, t4, t5, t6)			\

	SYSCALL_PT_ARG5(m, t1, t2, t3, t4, t5), m(t6, (regs->bp))

#define SYSCALL_PT_ARG5(m, t1, t2, t3, t4, t5)				\

	SYSCALL_PT_ARG4(m, t1, t2, t3, t4),  m(t5, (regs->di))

#define SYSCALL_PT_ARG4(m, t1, t2, t3, t4)				\

	SYSCALL_PT_ARG3(m, t1, t2, t3),  m(t4, (regs->si))

#define SYSCALL_PT_ARG3(m, t1, t2, t3)					\

	SYSCALL_PT_ARG2(m, t1, t2), m(t3, (regs->dx))

#define SYSCALL_PT_ARG2(m, t1, t2)					\

	SYSCALL_PT_ARG1(m, t1), m(t2, (regs->cx))

#define SYSCALL_PT_ARG1(m, t1) m(t1, (regs->bx))

#define SYSCALL_PT_ARGS(x, ...) SYSCALL_PT_ARG##x(__VA_ARGS__)



#define __SC_COMPAT_CAST(t, a)						\

	(__typeof(__builtin_choose_expr(__TYPE_IS_L(t), 0, 0U)))	\

	(unsigned int)a



/* Mapping of registers to parameters for syscalls on i386 */

#define SC_IA32_REGS_TO_ARGS(x, ...)					\

	__MAP(x,__SC_ARGS						\

	      ,,(unsigned int)regs->bx,,(unsigned int)regs->cx		\

	      ,,(unsigned int)regs->dx,,(unsigned int)regs->si		\

	      ,,(unsigned int)regs->di,,(unsigned int)regs->bp)

	SYSCALL_PT_ARGS(x, __SC_COMPAT_CAST,				\

			__MAP(x, __SC_TYPE, __VA_ARGS__))		\



#define __SYS_STUB0(abi, name)						\

	long __##abi##_##name(const struct pt_regs *regs);		\

arch/x86/kernel/alternative.c

+1 −1
Original line number Diff line number Diff line
@@ -403,7 +403,7 @@ noinstr void BUG_func(void) 
{

	BUG();

}

EXPORT_SYMBOL_GPL(BUG_func);

EXPORT_SYMBOL(BUG_func);



#define CALL_RIP_REL_OPCODE	0xff

#define CALL_RIP_REL_MODRM	0x15

arch/x86/kernel/cpu/amd.c

+24 −4
Original line number Diff line number Diff line
@@ -538,7 +538,7 @@ static void bsp_init_amd(struct cpuinfo_x86 *c) 


	/* Figure out Zen generations: */

	switch (c->x86) {

	case 0x17: {

	case 0x17:

		switch (c->x86_model) {

		case 0x00 ... 0x2f:

		case 0x50 ... 0x5f:
@@ -554,8 +554,8 @@ static void bsp_init_amd(struct cpuinfo_x86 *c) 
			goto warn;

		}

		break;

	}

	case 0x19: {



	case 0x19:

		switch (c->x86_model) {

		case 0x00 ... 0x0f:

		case 0x20 ... 0x5f:
@@ -569,7 +569,20 @@ static void bsp_init_amd(struct cpuinfo_x86 *c) 
			goto warn;

		}

		break;



	case 0x1a:

		switch (c->x86_model) {

		case 0x00 ... 0x0f:

		case 0x20 ... 0x2f:

		case 0x40 ... 0x4f:

		case 0x70 ... 0x7f:

			setup_force_cpu_cap(X86_FEATURE_ZEN5);

			break;

		default:

			goto warn;

		}

		break;



	default:

		break;

	}
@@ -1039,6 +1052,11 @@ static void init_amd_zen4(struct cpuinfo_x86 *c) 
		msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT);

}



static void init_amd_zen5(struct cpuinfo_x86 *c)

{

	init_amd_zen_common();

}



static void init_amd(struct cpuinfo_x86 *c)

{

	u64 vm_cr;
@@ -1084,6 +1102,8 @@ static void init_amd(struct cpuinfo_x86 *c) 
		init_amd_zen3(c);

	else if (boot_cpu_has(X86_FEATURE_ZEN4))

		init_amd_zen4(c);

	else if (boot_cpu_has(X86_FEATURE_ZEN5))

		init_amd_zen5(c);



	/*

	 * Enable workaround for FXSAVE leak on CPUs