Commit 9d498cce authored by Allen-KH Cheng's avatar Allen-KH Cheng Committed by Matthias Brugger
Browse files

arm64: dts: mediatek: Add cpufreq nodes for MT8192 



Add the cpufreq nodes for MT8192 SoC.

Signed-off-by: default avatarAllen-KH Cheng <allen-kh.cheng@mediatek.com>
Tested-by: default avatarChen-Yu Tsai <wenst@chromium.org>
Reviewed-by: default avatarNícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: default avatarNícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230317061944.15434-1-allen-kh.cheng@mediatek.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 6322555d

arch/arm64/boot/dts/mediatek/mt8192.dtsi

+14 −0
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ cpu0: cpu@0 { 
			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&l2_0>;

			performance-domains = <&performance 0>;

			capacity-dmips-mhz = <530>;

		};
@@ -87,6 +88,7 @@ cpu1: cpu@100 { 
			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&l2_0>;

			performance-domains = <&performance 0>;

			capacity-dmips-mhz = <530>;

		};
@@ -104,6 +106,7 @@ cpu2: cpu@200 { 
			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&l2_0>;

			performance-domains = <&performance 0>;

			capacity-dmips-mhz = <530>;

		};
@@ -121,6 +124,7 @@ cpu3: cpu@300 { 
			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&l2_0>;

			performance-domains = <&performance 0>;

			capacity-dmips-mhz = <530>;

		};
@@ -138,6 +142,7 @@ cpu4: cpu@400 { 
			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2_1>;

			performance-domains = <&performance 1>;

			capacity-dmips-mhz = <1024>;

		};
@@ -155,6 +160,7 @@ cpu5: cpu@500 { 
			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2_1>;

			performance-domains = <&performance 1>;

			capacity-dmips-mhz = <1024>;

		};
@@ -172,6 +178,7 @@ cpu6: cpu@600 { 
			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2_1>;

			performance-domains = <&performance 1>;

			capacity-dmips-mhz = <1024>;

		};
@@ -189,6 +196,7 @@ cpu7: cpu@700 { 
			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2_1>;

			performance-domains = <&performance 1>;

			capacity-dmips-mhz = <1024>;

		};
@@ -405,6 +413,12 @@ soc { 
		compatible = "simple-bus";

		ranges;



		performance: performance-controller@11bc10 {

			compatible = "mediatek,cpufreq-hw";

			reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;

			#performance-domain-cells = <1>;

		};



		gic: interrupt-controller@c000000 {

			compatible = "arm,gic-v3";

			#interrupt-cells = <4>;