Commit 9d6b6789 authored by Anshuman Khandual's avatar Anshuman Khandual Committed by Catalin Marinas
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arm64/hw_breakpoint: Directly use ESR_ELx_WNR for an watchpoint exception 



Let's use existing ISS encoding for an watchpoint exception i.e ESR_ELx_WNR
This represents an instruction's either writing to or reading from a memory
location during an watchpoint exception. While here this drops non-standard
macro AARCH64_ESR_ACCESS_MASK.

Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: default avatarMark Brown <broonie@kernel.org>
Signed-off-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20240229083431.356578-1-anshuman.khandual@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 62244266

arch/arm64/include/asm/hw_breakpoint.h

+0 −1
Original line number Diff line number Diff line
@@ -59,7 +59,6 @@ static inline void decode_ctrl_reg(u32 reg, 
/* Watchpoints */

#define ARM_BREAKPOINT_LOAD	1

#define ARM_BREAKPOINT_STORE	2

#define AARCH64_ESR_ACCESS_MASK	(1 << 6)



/* Lengths */

#define ARM_BREAKPOINT_LEN_1	0x1

arch/arm64/kernel/hw_breakpoint.c

+2 −1
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 


#include <asm/current.h>

#include <asm/debug-monitors.h>

#include <asm/esr.h>

#include <asm/hw_breakpoint.h>

#include <asm/traps.h>

#include <asm/cputype.h>
@@ -779,7 +780,7 @@ static int watchpoint_handler(unsigned long addr, unsigned long esr, 
		 * Check that the access type matches.

		 * 0 => load, otherwise => store

		 */

		access = (esr & AARCH64_ESR_ACCESS_MASK) ? HW_BREAKPOINT_W :

		access = (esr & ESR_ELx_WNR) ? HW_BREAKPOINT_W :

			 HW_BREAKPOINT_R;

		if (!(access & hw_breakpoint_type(wp)))

			continue;