Commit 9da1c032 authored by Uwe Kleine-König's avatar Uwe Kleine-König Committed by Heiko Stuebner
Browse files

arm64: dts: rockchip: Add basic support for QNAP TS-433 



This is enough to make eMMC, networking, UART (console), RTC and a hard
disk accessible. Still missing are (at least): USB, LEDs, regulators,
fan.

Signed-off-by: default avatarUwe Kleine-König <ukleinek@debian.org>
Link: https://lore.kernel.org/r/0d9fa5d730ac1cb91261b25b6809fcef3a12f03a.1709034476.git.ukleinek@debian.org


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 0660dd95

arch/arm64/boot/dts/rockchip/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -103,6 +103,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb 
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb

dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb

dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb

dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts433.dtb

dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb

dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb

dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb

arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts

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+86 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.

 * Copyright (c) 2024 Uwe Kleine-König

 */



/dts-v1/;



#include <dt-bindings/gpio/gpio.h>

#include "rk3568.dtsi"



/ {

	model = "Qnap TS-433-4G NAS System 4-Bay";

	compatible = "qnap,ts433", "rockchip,rk3568";

};



&gmac0 {

	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;

	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;

	assigned-clock-rates = <0>, <125000000>;

	clock_in_out = "output";

	phy-handle = <&rgmii_phy0>;

	phy-mode = "rgmii";

	pinctrl-names = "default";

	pinctrl-0 = <&gmac0_miim

		     &gmac0_tx_bus2

		     &gmac0_rx_bus2

		     &gmac0_rgmii_clk

		     &gmac0_rgmii_bus>;

	rx_delay = <0x2f>;

	tx_delay = <0x3c>;

	status = "okay";

};



&i2c0 {

	pmic@20 {

		compatible = "rockchip,rk809";

		reg = <0x20>;

		interrupt-parent = <&gpio0>;

		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;

	};

};



&i2c1 {

	status = "okay";



	rtc@51 {

		compatible = "microcrystal,rv8263";

		reg = <0x51>;

		wakeup-source;

	};

};



&mdio0 {

	rgmii_phy0: ethernet-phy@0 {

		compatible = "ethernet-phy-ieee802.3-c22";

		reg = <0x0>;

	};

};



&pcie30phy {

	status = "okay";

};



&pcie3x1 {

	/* The downstream dts has: rockchip,bifurcation, XXX: find out what this is about */

	reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;

	status = "okay";

};



&sdhci {

	bus-width = <8>;

	max-frequency = <200000000>;

	non-removable;

	status = "okay";

};



/*

 * Pins available on CN2 connector at TTL voltage level (3V3).

 * ,_  _.

 * |1234|  1=TX 2=VCC

 * `----'  3=RX 4=GND

 */

&uart2 {

	status = "okay";

};