Commit 9dab00ee authored by Abel Vesa's avatar Abel Vesa Committed by Vinod Koul
Browse files

phy: qcom: qmp-pcie: Add Gen4 4-lanes mode for X1E80100 



The sixth PCIe controller on X1E80100 can be used in either
4-lanes mode or 2-lanes mode. Add the configuration and compatible
for the 4-lane mode.

Reviewed-by: default avatarJohan Hovold <johan+linaro@kernel.org>
Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Tested-by: default avatarJohan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20240823-x1e80100-phy-add-gen4x4-v3-2-b7765631ca01@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 0c5f4d23

drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

+42 −0
Original line number Diff line number Diff line
@@ -1242,6 +1242,10 @@ static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_serdes_tbl[] = { 
	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f),

};



static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x1c),

};



static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88),
@@ -3645,6 +3649,41 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = { 
		.ln_shrd		= x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl,

		.ln_shrd_num		= ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl),

	},



	.reset_list		= sdm845_pciephy_reset_l,

	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),

	.vreg_list		= sm8550_qmp_phy_vreg_l,

	.num_vregs		= ARRAY_SIZE(sm8550_qmp_phy_vreg_l),

	.regs			= pciephy_v6_regs_layout,



	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,

	.phy_status		= PHYSTATUS_4_20,

	.has_nocsr_reset	= true,

};



static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = {

	.lanes = 4,



	.offsets		= &qmp_pcie_offsets_v6_20,



	.tbls = {

		.serdes			= x1e80100_qmp_gen4x2_pcie_serdes_tbl,

		.serdes_num		= ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_serdes_tbl),

		.tx			= x1e80100_qmp_gen4x2_pcie_tx_tbl,

		.tx_num			= ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_tx_tbl),

		.rx			= x1e80100_qmp_gen4x2_pcie_rx_tbl,

		.rx_num			= ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_rx_tbl),

		.pcs			= x1e80100_qmp_gen4x2_pcie_pcs_tbl,

		.pcs_num		= ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_tbl),

		.pcs_misc		= x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl,

		.pcs_misc_num		= ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl),

		.ln_shrd		= x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl,

		.ln_shrd_num		= ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl),

	},



	.serdes_4ln_tbl		= x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl,

	.serdes_4ln_num		= ARRAY_SIZE(x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl),



	.reset_list		= sdm845_pciephy_reset_l,

	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),

	.vreg_list		= sm8550_qmp_phy_vreg_l,
@@ -4415,6 +4454,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { 
	}, {

		.compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy",

		.data = &x1e80100_qmp_gen4x2_pciephy_cfg,

	}, {

		.compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy",

		.data = &x1e80100_qmp_gen4x4_pciephy_cfg,

	},

	{ },

};