Commit 9dab15b1 authored by Rasmus Villemoes's avatar Rasmus Villemoes Committed by Li Yang
Browse files

soc: fsl: qe: merge qe_ic.h headers into qe_ic.c 



The public qe_ic.h header is no longer included by anything but
qe_ic.c. Merge both headers into qe_ic.c, and drop the unused
constants.

Reviewed-by: default avatarTimur Tabi <timur@kernel.org>
Signed-off-by: default avatarRasmus Villemoes <linux@rasmusvillemoes.dk>
Signed-off-by: default avatarLi Yang <leoyang.li@nxp.com>
parent 882c626d

drivers/soc/fsl/qe/qe_ic.c

+50 −2
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include <linux/kernel.h>

#include <linux/init.h>

#include <linux/errno.h>

#include <linux/irq.h>

#include <linux/reboot.h>

#include <linux/slab.h>

#include <linux/stddef.h>
@@ -25,9 +26,56 @@ 
#include <asm/irq.h>

#include <asm/io.h>

#include <soc/fsl/qe/qe.h>

#include <soc/fsl/qe/qe_ic.h>



#include "qe_ic.h"

#define NR_QE_IC_INTS		64



/* QE IC registers offset */

#define QEIC_CICR		0x00

#define QEIC_CIVEC		0x04

#define QEIC_CIPXCC		0x10

#define QEIC_CIPYCC		0x14

#define QEIC_CIPWCC		0x18

#define QEIC_CIPZCC		0x1c

#define QEIC_CIMR		0x20

#define QEIC_CRIMR		0x24

#define QEIC_CIPRTA		0x30

#define QEIC_CIPRTB		0x34

#define QEIC_CHIVEC		0x60



struct qe_ic {

	/* Control registers offset */

	u32 __iomem *regs;



	/* The remapper for this QEIC */

	struct irq_domain *irqhost;



	/* The "linux" controller struct */

	struct irq_chip hc_irq;



	/* VIRQ numbers of QE high/low irqs */

	unsigned int virq_high;

	unsigned int virq_low;

};



/*

 * QE interrupt controller internal structure

 */

struct qe_ic_info {

	/* Location of this source at the QIMR register */

	u32	mask;



	/* Mask register offset */

	u32	mask_reg;



	/*

	 * For grouped interrupts sources - the interrupt code as

	 * appears at the group priority register

	 */

	u8	pri_code;



	/* Group priority register offset */

	u32	pri_reg;

};



static DEFINE_RAW_SPINLOCK(qe_ic_lock);

drivers/soc/fsl/qe/qe_ic.h

deleted100644 → 0
+0 −99
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-or-later */

/*

 * drivers/soc/fsl/qe/qe_ic.h

 *

 * QUICC ENGINE Interrupt Controller Header

 *

 * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.

 *

 * Author: Li Yang <leoli@freescale.com>

 * Based on code from Shlomi Gridish <gridish@freescale.com>

 */

#ifndef _POWERPC_SYSDEV_QE_IC_H

#define _POWERPC_SYSDEV_QE_IC_H



#include <soc/fsl/qe/qe_ic.h>



#define NR_QE_IC_INTS		64



/* QE IC registers offset */

#define QEIC_CICR		0x00

#define QEIC_CIVEC		0x04

#define QEIC_CRIPNR		0x08

#define QEIC_CIPNR		0x0c

#define QEIC_CIPXCC		0x10

#define QEIC_CIPYCC		0x14

#define QEIC_CIPWCC		0x18

#define QEIC_CIPZCC		0x1c

#define QEIC_CIMR		0x20

#define QEIC_CRIMR		0x24

#define QEIC_CICNR		0x28

#define QEIC_CIPRTA		0x30

#define QEIC_CIPRTB		0x34

#define QEIC_CRICR		0x3c

#define QEIC_CHIVEC		0x60



/* Interrupt priority registers */

#define CIPCC_SHIFT_PRI0	29

#define CIPCC_SHIFT_PRI1	26

#define CIPCC_SHIFT_PRI2	23

#define CIPCC_SHIFT_PRI3	20

#define CIPCC_SHIFT_PRI4	13

#define CIPCC_SHIFT_PRI5	10

#define CIPCC_SHIFT_PRI6	7

#define CIPCC_SHIFT_PRI7	4



/* CICR priority modes */

#define CICR_GWCC		0x00040000

#define CICR_GXCC		0x00020000

#define CICR_GYCC		0x00010000

#define CICR_GZCC		0x00080000

#define CICR_GRTA		0x00200000

#define CICR_GRTB		0x00400000

#define CICR_HPIT_SHIFT		8

#define CICR_HPIT_MASK		0x00000300

#define CICR_HP_SHIFT		24

#define CICR_HP_MASK		0x3f000000



/* CICNR */

#define CICNR_WCC1T_SHIFT	20

#define CICNR_ZCC1T_SHIFT	28

#define CICNR_YCC1T_SHIFT	12

#define CICNR_XCC1T_SHIFT	4



/* CRICR */

#define CRICR_RTA1T_SHIFT	20

#define CRICR_RTB1T_SHIFT	28



/* Signal indicator */

#define SIGNAL_MASK		3

#define SIGNAL_HIGH		2

#define SIGNAL_LOW		0



struct qe_ic {

	/* Control registers offset */

	u32 __iomem *regs;



	/* The remapper for this QEIC */

	struct irq_domain *irqhost;



	/* The "linux" controller struct */

	struct irq_chip hc_irq;



	/* VIRQ numbers of QE high/low irqs */

	unsigned int virq_high;

	unsigned int virq_low;

};



/*

 * QE interrupt controller internal structure

 */

struct qe_ic_info {

	u32	mask;	  /* location of this source at the QIMR register. */

	u32	mask_reg; /* Mask register offset */

	u8	pri_code; /* for grouped interrupts sources - the interrupt

			     code as appears at the group priority register */

	u32	pri_reg;  /* Group priority register offset */

};



#endif /* _POWERPC_SYSDEV_QE_IC_H */

include/soc/fsl/qe/qe_ic.h

deleted100644 → 0
+0 −56
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-or-later */

/*

 * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.

 *

 * Authors: 	Shlomi Gridish <gridish@freescale.com>

 * 		Li Yang <leoli@freescale.com>

 *

 * Description:

 * QE IC external definitions and structure.

 */

#ifndef _ASM_POWERPC_QE_IC_H

#define _ASM_POWERPC_QE_IC_H



#include <linux/irq.h>



struct device_node;

struct qe_ic;



#define NUM_OF_QE_IC_GROUPS	6



/* Flags when we init the QE IC */

#define QE_IC_SPREADMODE_GRP_W			0x00000001

#define QE_IC_SPREADMODE_GRP_X			0x00000002

#define QE_IC_SPREADMODE_GRP_Y			0x00000004

#define QE_IC_SPREADMODE_GRP_Z			0x00000008

#define QE_IC_SPREADMODE_GRP_RISCA		0x00000010

#define QE_IC_SPREADMODE_GRP_RISCB		0x00000020



#define QE_IC_LOW_SIGNAL			0x00000100

#define QE_IC_HIGH_SIGNAL			0x00000200



#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH	0x00001000

#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH	0x00002000

#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH	0x00004000

#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH	0x00008000

#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH	0x00010000

#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH	0x00020000

#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH	0x00040000

#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH	0x00080000

#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH	0x00100000

#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH	0x00200000

#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH	0x00400000

#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH	0x00800000

#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT		(12)



/* QE interrupt sources groups */

enum qe_ic_grp_id {

	QE_IC_GRP_W = 0,	/* QE interrupt controller group W */

	QE_IC_GRP_X,		/* QE interrupt controller group X */

	QE_IC_GRP_Y,		/* QE interrupt controller group Y */

	QE_IC_GRP_Z,		/* QE interrupt controller group Z */

	QE_IC_GRP_RISCA,	/* QE interrupt controller RISC group A */

	QE_IC_GRP_RISCB		/* QE interrupt controller RISC group B */

};



#endif /* _ASM_POWERPC_QE_IC_H */