Commit 9dbaf381 authored by Mayuresh Chitale's avatar Mayuresh Chitale Committed by Anup Patel
Browse files

RISC-V: Detect Smstateen extension 



Extend the ISA string parsing to detect the Smstateen extension. If the
extension is enabled then access to certain 'state' such as AIA CSRs in
VS mode is controlled by *stateen0 registers.

Signed-off-by: default avatarMayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent 94f6f055

arch/riscv/include/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -58,6 +58,7 @@ 
#define RISCV_ISA_EXT_ZICSR		40

#define RISCV_ISA_EXT_ZIFENCEI		41

#define RISCV_ISA_EXT_ZIHPM		42

#define RISCV_ISA_EXT_SMSTATEEN		43



#define RISCV_ISA_EXT_MAX		64

arch/riscv/kernel/cpufeature.c

+1 −0
Original line number Diff line number Diff line
@@ -175,6 +175,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { 
	__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),

	__RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),

	__RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),

	__RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),

	__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),

	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),

	__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),