Commit 9dd56e97 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915/lvds: Use REG_BIT() & co. 



Use REG_BIT() & co. for the LVDS port register.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230130180540.8972-4-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 2324cdff

drivers/gpu/drm/i915/display/intel_lvds.c

+2 −2
Original line number Diff line number Diff line
@@ -93,9 +93,9 @@ bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv, 


	/* asserts want to know the pipe even if the port is disabled */

	if (HAS_PCH_CPT(dev_priv))

		*pipe = (val & LVDS_PIPE_SEL_MASK_CPT) >> LVDS_PIPE_SEL_SHIFT_CPT;

		*pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK_CPT, val);

	else

		*pipe = (val & LVDS_PIPE_SEL_MASK) >> LVDS_PIPE_SEL_SHIFT;

		*pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK, val);



	return val & LVDS_PORT_EN;

}

drivers/gpu/drm/i915/i915_reg.h

+22 −24
Original line number Diff line number Diff line
@@ -2603,52 +2603,50 @@ 
 * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as

 * the DPLL semantics change when the LVDS is assigned to that pipe.

 */

#define   LVDS_PORT_EN			(1 << 31)

#define   LVDS_PORT_EN			REG_BIT(31)

/* Selects pipe B for LVDS data.  Must be set on pre-965. */

#define   LVDS_PIPE_SEL_SHIFT		30

#define   LVDS_PIPE_SEL_MASK		(1 << 30)

#define   LVDS_PIPE_SEL(pipe)		((pipe) << 30)

#define   LVDS_PIPE_SEL_SHIFT_CPT	29

#define   LVDS_PIPE_SEL_MASK_CPT	(3 << 29)

#define   LVDS_PIPE_SEL_CPT(pipe)	((pipe) << 29)

#define   LVDS_PIPE_SEL_MASK		REG_BIT(30)

#define   LVDS_PIPE_SEL(pipe)		REG_FIELD_PREP(LVDS_PIPE_SEL_MASK, (pipe))

#define   LVDS_PIPE_SEL_MASK_CPT	REG_GENMASK(30, 29)

#define   LVDS_PIPE_SEL_CPT(pipe)	REG_FIELD_PREP(LVDS_PIPE_SEL_MASK_CPT, (pipe))

/* LVDS dithering flag on 965/g4x platform */

#define   LVDS_ENABLE_DITHER		(1 << 25)

#define   LVDS_ENABLE_DITHER		REG_BIT(25)

/* LVDS sync polarity flags. Set to invert (i.e. negative) */

#define   LVDS_VSYNC_POLARITY		(1 << 21)

#define   LVDS_HSYNC_POLARITY		(1 << 20)

#define   LVDS_VSYNC_POLARITY		REG_BIT(21)

#define   LVDS_HSYNC_POLARITY		REG_BIT(20)



/* Enable border for unscaled (or aspect-scaled) display */

#define   LVDS_BORDER_ENABLE		(1 << 15)

#define   LVDS_BORDER_ENABLE		REG_BIT(15)

/*

 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per

 * pixel.

 */

#define   LVDS_A0A2_CLKA_POWER_MASK	(3 << 8)

#define   LVDS_A0A2_CLKA_POWER_DOWN	(0 << 8)

#define   LVDS_A0A2_CLKA_POWER_UP	(3 << 8)

#define   LVDS_A0A2_CLKA_POWER_MASK	REG_GENMASK(9, 8)

#define   LVDS_A0A2_CLKA_POWER_DOWN	REG_FIELD_PREP(LVDS_A0A2_CLKA_POWER_MASK, 0)

#define   LVDS_A0A2_CLKA_POWER_UP	REG_FIELD_PREP(LVDS_A0A2_CLKA_POWER_MASK, 3)

/*

 * Controls the A3 data pair, which contains the additional LSBs for 24 bit

 * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be

 * on.

 */

#define   LVDS_A3_POWER_MASK		(3 << 6)

#define   LVDS_A3_POWER_DOWN		(0 << 6)

#define   LVDS_A3_POWER_UP		(3 << 6)

#define   LVDS_A3_POWER_MASK		REG_GENMASK(7, 6)

#define   LVDS_A3_POWER_DOWN		REG_FIELD_PREP(LVDS_A3_POWER_MASK, 0)

#define   LVDS_A3_POWER_UP		REG_FIELD_PREP(LVDS_A3_POWER_MASK, 3)

/*

 * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP

 * is set.

 */

#define   LVDS_CLKB_POWER_MASK		(3 << 4)

#define   LVDS_CLKB_POWER_DOWN		(0 << 4)

#define   LVDS_CLKB_POWER_UP		(3 << 4)

#define   LVDS_CLKB_POWER_MASK		REG_GENMASK(5, 4)

#define   LVDS_CLKB_POWER_DOWN		REG_FIELD_PREP(LVDS_CLKB_POWER_MASK, 0)

#define   LVDS_CLKB_POWER_UP		REG_FIELD_PREP(LVDS_CLKB_POWER_MASK, 3)

/*

 * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2

 * setting for whether we are in dual-channel mode.  The B3 pair will

 * additionally only be powered up when LVDS_A3_POWER_UP is set.

 */

#define   LVDS_B0B3_POWER_MASK		(3 << 2)

#define   LVDS_B0B3_POWER_DOWN		(0 << 2)

#define   LVDS_B0B3_POWER_UP		(3 << 2)

#define   LVDS_B0B3_POWER_MASK		REG_GENMASK(3, 2)

#define   LVDS_B0B3_POWER_DOWN		REG_FIELD_PREP(LVDS_B0B3_POWER_MASK, 0)

#define   LVDS_B0B3_POWER_UP		REG_FIELD_PREP(LVDS_B0B3_POWER_MASK, 3)



/* Video Data Island Packet control */

#define VIDEO_DIP_DATA		_MMIO(0x61178)
@@ -6398,7 +6396,7 @@ 
#define FDI_PLL_CTL_2           _MMIO(0xfe004)



#define PCH_LVDS	_MMIO(0xe1180)

#define  LVDS_DETECTED	(1 << 1)

#define   LVDS_DETECTED	REG_BIT(1)



#define _PCH_DP_B		0xe4100

#define PCH_DP_B		_MMIO(_PCH_DP_B)