Commit 9de60462 authored by Michael Strauss's avatar Michael Strauss Committed by Alex Deucher
Browse files

drm/amd/display: Update HPO I/O When Handling Link Retrain Automation Request 



[WHY]
Previous multi-display HPO fix moved where HPO I/O enable/disable is performed.
The codepath now taken to enable/disable HPO I/O is not used for compliance
test automation, meaning that if a compliance box being driven at a DP1 rate
requests retrain at UHBR, HPO I/O will remain off if it was previously off.

[HOW]
Explicitly update HPO I/O after allocating encoders for test request.

Reviewed-by: default avatarCharlene Liu <charlene.liu@amd.com>
Reviewed-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Signed-off-by: default avatarMichael Strauss <michael.strauss@amd.com>
Signed-off-by: default avatarRoman Li <roman.li@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 18ac82c2

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+13 −0
Original line number Diff line number Diff line
@@ -5303,3 +5303,16 @@ int resource_calculate_det_for_stream(struct dc_state *state, struct pipe_ctx *o 
	}

	return det_segments;

}



bool resource_is_hpo_acquired(struct dc_state *context)

{

	int i;



	for (i = 0; i < MAX_HPO_DP2_ENCODERS; i++) {

		if (context->res_ctx.is_hpo_dp_stream_enc_acquired[i]) {

			return true;

		}

	}



	return false;

}

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

+4 −17
Original line number Diff line number Diff line
@@ -2350,19 +2350,6 @@ static void dce110_setup_audio_dto( 
	}

}



static bool dce110_is_hpo_enabled(struct dc_state *context)

{

	int i;



	for (i = 0; i < MAX_HPO_DP2_ENCODERS; i++) {

		if (context->res_ctx.is_hpo_dp_stream_enc_acquired[i]) {

			return true;

		}

	}



	return false;

}



enum dc_status dce110_apply_ctx_to_hw(

		struct dc *dc,

		struct dc_state *context)
@@ -2371,8 +2358,8 @@ enum dc_status dce110_apply_ctx_to_hw( 
	struct dc_bios *dcb = dc->ctx->dc_bios;

	enum dc_status status;

	int i;

	bool was_hpo_enabled = dce110_is_hpo_enabled(dc->current_state);

	bool is_hpo_enabled = dce110_is_hpo_enabled(context);

	bool was_hpo_acquired = resource_is_hpo_acquired(dc->current_state);

	bool is_hpo_acquired = resource_is_hpo_acquired(context);



	/* reset syncd pipes from disabled pipes */

	if (dc->config.use_pipe_ctx_sync_logic)
@@ -2415,8 +2402,8 @@ enum dc_status dce110_apply_ctx_to_hw( 


	dce110_setup_audio_dto(dc, context);



	if (dc->hwseq->funcs.setup_hpo_hw_control && was_hpo_enabled != is_hpo_enabled) {

		dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, is_hpo_enabled);

	if (dc->hwseq->funcs.setup_hpo_hw_control && was_hpo_acquired != is_hpo_acquired) {

		dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, is_hpo_acquired);

	}



	for (i = 0; i < dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c

+1 −0
Original line number Diff line number Diff line
@@ -111,6 +111,7 @@ static const struct hw_sequencer_funcs dcn31_funcs = { 
	.optimize_pwr_state = dcn21_optimize_pwr_state,

	.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,

	.update_visual_confirm_color = dcn10_update_visual_confirm_color,

	.setup_hpo_hw_control = dcn31_setup_hpo_hw_control,

};



static const struct hwseq_private_funcs dcn31_private_funcs = {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c

+1 −0
Original line number Diff line number Diff line
@@ -114,6 +114,7 @@ static const struct hw_sequencer_funcs dcn314_funcs = { 
	.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,

	.update_visual_confirm_color = dcn10_update_visual_confirm_color,

	.calculate_pix_rate_divider = dcn314_calculate_pix_rate_divider,

	.setup_hpo_hw_control = dcn31_setup_hpo_hw_control,

};



static const struct hwseq_private_funcs dcn314_private_funcs = {

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c

+1 −0
Original line number Diff line number Diff line
@@ -123,6 +123,7 @@ static const struct hw_sequencer_funcs dcn351_funcs = { 
	.set_long_vtotal = dcn35_set_long_vblank,

	.calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider,

	.program_outstanding_updates = dcn32_program_outstanding_updates,

	.setup_hpo_hw_control = dcn35_setup_hpo_hw_control,

};



static const struct hwseq_private_funcs dcn351_private_funcs = {