Commit 9e0794ae authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'mtk-dts64-fixes-for-v6.9' of... 

Merge tag 'mtk-dts64-fixes-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into for-next

MediaTek ARM64 DTS fixes for v6.9

This fixes some dts validation issues against bindings for multiple SoCs,
GPU voltage constraints for Chromebook devices, missing gce-client-reg
on various nodes (performance issues) on MT8183/92/95, and also fixes
boot issues on MT8195 when SPMI is built as module.

* tag 'mtk-dts64-fixes-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
  arm64: dts: mediatek: mt2712: fix validation errors
  arm64: dts: mediatek: mt7986: prefix BPI-R3 cooling maps with "map-"
  arm64: dts: mediatek: mt7986: drop invalid thermal block clock
  arm64: dts: mediatek: mt7986: drop "#reset-cells" from Ethernet controller
  arm64: dts: mediatek: mt7986: drop invalid properties from ethsys
  arm64: dts: mediatek: mt7622: drop "reset-names" from thermal block
  arm64: dts: mediatek: mt7622: fix ethernet controller "compatible"
  arm64: dts: mediatek: mt7622: fix IR nodename
  arm64: dts: mediatek: mt7622: fix clock controllers
  arm64: dts: mediatek: mt8186-corsola: Update min voltage constraint for Vgpu
  arm64: dts: mediatek: mt8183-kukui: Use default min voltage for MT6358
  arm64: dts: mediatek: mt8195-cherry: Update min voltage constraint for MT6315
  arm64: dts: mediatek: mt8192-asurada: Update min voltage constraint for MT6315
  arm64: dts: mediatek: cherry: Describe CPU supplies
  arm64: dts: mediatek: mt8195: Add missing gce-client-reg to mutex1
  arm64: dts: mediatek: mt8195: Add missing gce-client-reg to mutex
  arm64: dts: mediatek: mt8195: Add missing gce-client-reg to vpp/vdosys
  arm64: dts: mediatek: mt8192: Add missing gce-client-reg to mutex
  arm64: dts: mediatek: mt8183: Add power-domains properity to mfgcfg
parents fdabd4b2 3baac729

arch/arm64/boot/dts/mediatek/mt2712-evb.dts

+4 −4
Original line number Diff line number Diff line
@@ -129,7 +129,7 @@ ethernet_phy0: ethernet-phy@5 { 
};



&pio {

	eth_default: eth_default {

	eth_default: eth-default-pins {

		tx_pins {

			pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GBE_TXD3>,

				 <MT2712_PIN_72_GBE_TXD2__FUNC_GBE_TXD2>,
@@ -156,7 +156,7 @@ mdio_pins { 
		};

	};



	eth_sleep: eth_sleep {

	eth_sleep: eth-sleep-pins {

		tx_pins {

			pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GPIO71>,

				 <MT2712_PIN_72_GBE_TXD2__FUNC_GPIO72>,
@@ -182,14 +182,14 @@ mdio_pins { 
		};

	};



	usb0_id_pins_float: usb0_iddig {

	usb0_id_pins_float: usb0-iddig-pins {

		pins_iddig {

			pinmux = <MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A>;

			bias-pull-up;

		};

	};



	usb1_id_pins_float: usb1_iddig {

	usb1_id_pins_float: usb1-iddig-pins {

		pins_iddig {

			pinmux = <MT2712_PIN_14_IDDIG_P1__FUNC_IDDIG_B>;

			bias-pull-up;

arch/arm64/boot/dts/mediatek/mt2712e.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -249,10 +249,11 @@ topckgen: syscon@10000000 { 
		#clock-cells = <1>;

	};



	infracfg: syscon@10001000 {

	infracfg: clock-controller@10001000 {

		compatible = "mediatek,mt2712-infracfg", "syscon";

		reg = <0 0x10001000 0 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	pericfg: syscon@10003000 {

arch/arm64/boot/dts/mediatek/mt7622.dtsi

+14 −20
Original line number Diff line number Diff line
@@ -252,7 +252,7 @@ scpsys: power-controller@10006000 { 
		clock-names = "hif_sel";

	};



	cir: cir@10009000 {

	cir: ir-receiver@10009000 {

		compatible = "mediatek,mt7622-cir";

		reg = <0 0x10009000 0 0x1000>;

		interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
@@ -283,16 +283,14 @@ thermal_calibration: calib@198 { 
		};

	};



	apmixedsys: apmixedsys@10209000 {

		compatible = "mediatek,mt7622-apmixedsys",

			     "syscon";

	apmixedsys: clock-controller@10209000 {

		compatible = "mediatek,mt7622-apmixedsys";

		reg = <0 0x10209000 0 0x1000>;

		#clock-cells = <1>;

	};



	topckgen: topckgen@10210000 {

		compatible = "mediatek,mt7622-topckgen",

			     "syscon";

	topckgen: clock-controller@10210000 {

		compatible = "mediatek,mt7622-topckgen";

		reg = <0 0x10210000 0 0x1000>;

		#clock-cells = <1>;

	};
@@ -515,7 +513,6 @@ thermal: thermal@1100b000 { 
			 <&pericfg CLK_PERI_AUXADC_PD>;

		clock-names = "therm", "auxadc";

		resets = <&pericfg MT7622_PERI_THERM_SW_RST>;

		reset-names = "therm";

		mediatek,auxadc = <&auxadc>;

		mediatek,apmixedsys = <&apmixedsys>;

		nvmem-cells = <&thermal_calibration>;
@@ -734,9 +731,8 @@ wmac: wmac@18000000 { 
		power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;

	};



	ssusbsys: ssusbsys@1a000000 {

		compatible = "mediatek,mt7622-ssusbsys",

			     "syscon";

	ssusbsys: clock-controller@1a000000 {

		compatible = "mediatek,mt7622-ssusbsys";

		reg = <0 0x1a000000 0 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;
@@ -793,9 +789,8 @@ u2port1: usb-phy@1a0c5000 { 
		};

	};



	pciesys: pciesys@1a100800 {

		compatible = "mediatek,mt7622-pciesys",

			     "syscon";

	pciesys: clock-controller@1a100800 {

		compatible = "mediatek,mt7622-pciesys";

		reg = <0 0x1a100800 0 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;
@@ -921,12 +916,13 @@ sata_port: sata-phy@1a243000 { 
		};

	};



	hifsys: syscon@1af00000 {

		compatible = "mediatek,mt7622-hifsys", "syscon";

	hifsys: clock-controller@1af00000 {

		compatible = "mediatek,mt7622-hifsys";

		reg = <0 0x1af00000 0 0x70>;

		#clock-cells = <1>;

	};



	ethsys: syscon@1b000000 {

	ethsys: clock-controller@1b000000 {

		compatible = "mediatek,mt7622-ethsys",

			     "syscon";

		reg = <0 0x1b000000 0 0x1000>;
@@ -966,9 +962,7 @@ wed1: wed@1020b000 { 
	};



	eth: ethernet@1b100000 {

		compatible = "mediatek,mt7622-eth",

			     "mediatek,mt2701-eth",

			     "syscon";

		compatible = "mediatek,mt7622-eth";

		reg = <0 0x1b100000 0 0x20000>;

		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,

arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts

+3 −3
Original line number Diff line number Diff line
@@ -146,19 +146,19 @@ sfp2: sfp-2 { 


&cpu_thermal {

	cooling-maps {

		cpu-active-high {

		map-cpu-active-high {

			/* active: set fan to cooling level 2 */

			cooling-device = <&fan 2 2>;

			trip = <&cpu_trip_active_high>;

		};



		cpu-active-med {

		map-cpu-active-med {

			/* active: set fan to cooling level 1 */

			cooling-device = <&fan 1 1>;

			trip = <&cpu_trip_active_med>;

		};



		cpu-active-low {

		map-cpu-active-low {

			/* active: set fan to cooling level 0 */

			cooling-device = <&fan 0 0>;

			trip = <&cpu_trip_active_low>;

arch/arm64/boot/dts/mediatek/mt7986a.dtsi

+2 −6
Original line number Diff line number Diff line
@@ -332,9 +332,8 @@ thermal: thermal@1100c800 { 
			reg = <0 0x1100c800 0 0x800>;

			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&infracfg CLK_INFRA_THERM_CK>,

				 <&infracfg CLK_INFRA_ADC_26M_CK>,

				 <&infracfg CLK_INFRA_ADC_FRC_CK>;

			clock-names = "therm", "auxadc", "adc_32k";

				 <&infracfg CLK_INFRA_ADC_26M_CK>;

			clock-names = "therm", "auxadc";

			nvmem-cells = <&thermal_calibration>;

			nvmem-cell-names = "calibration-data";

			#thermal-sensor-cells = <1>;
@@ -492,8 +491,6 @@ ethsys: syscon@15000000 { 
			 compatible = "mediatek,mt7986-ethsys",

				      "syscon";

			 reg = <0 0x15000000 0 0x1000>;

			 #address-cells = <1>;

			 #size-cells = <1>;

			 #clock-cells = <1>;

			 #reset-cells = <1>;

		};
@@ -556,7 +553,6 @@ eth: ethernet@15100000 { 
					  <&topckgen CLK_TOP_SGM_325M_SEL>;

			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,

						 <&apmixedsys CLK_APMIXED_SGMPLL>;

			#reset-cells = <1>;

			#address-cells = <1>;

			#size-cells = <0>;

			mediatek,ethsys = <&ethsys>;