Commit 9e5889c6 authored by Claudiu Beznea's avatar Claudiu Beznea Committed by Geert Uytterhoeven
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pinctrl: renesas: rzg2l: Add input enable to the Ethernet pins 



Some of the RZ/G3S Ethernet pins (P1_0, P7_0) can be configured with
input enable.  Enable this functionality for these pins.

Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231207070700.4156557-8-claudiu.beznea.uj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 1bbc8ee4

drivers/pinctrl/renesas/pinctrl-rzg2l.c

+2 −2
Original line number Diff line number Diff line
@@ -1444,7 +1444,7 @@ static const u32 r9a08g045_gpio_configs[] = { 
	RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)),			/* P0  */

	RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |

								PIN_CFG_IO_VMC_ETH0)) |

				      PIN_CFG_OEN,					/* P1 */

				      PIN_CFG_OEN | PIN_CFG_IEN,			/* P1 */

	RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |

								PIN_CFG_IO_VMC_ETH0)),	/* P2 */

	RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
@@ -1455,7 +1455,7 @@ static const u32 r9a08g045_gpio_configs[] = { 
	RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)),			/* P6  */

	RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |

								PIN_CFG_IO_VMC_ETH1)) |

				      PIN_CFG_OEN,					/* P7 */

				      PIN_CFG_OEN | PIN_CFG_IEN,			/* P7 */

	RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |

								PIN_CFG_IO_VMC_ETH1)),	/* P8 */

	RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |