Commit 9e7acf70 authored Apr 14, 2025 by Vincent Knecht Committed by Bjorn Andersson May 14, 2025

clk: qcom: gcc-msm8939: Fix mclk0 & mclk1 for 24 MHz

Fix mclk0 & mclk1 parent map to use correct GPLL6 configuration and
freq_tbl to use GPLL6 instead of GPLL0 so that they tick at 24 MHz.

Fixes: 1664014e ("clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller")
Suggested-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org>
Link: https://lore.kernel.org/r/20250414-gcc-msm8939-fixes-mclk-v2-resend2-v2-1-5ddcf572a6de@mailoo.org

Signed-off-by: Bjorn Andersson <andersson@kernel.org>

parent a4e07dde

drivers/clk/qcom/gcc-msm8939.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -432,7 +432,7 @@ static const struct parent_map gcc_xo_gpll0_gpll1a_gpll6_sleep_map[] = {
		{ P_XO, 0 },
		{ P_GPLL0, 1 },
		{ P_GPLL1_AUX, 2 },
		{ P_GPLL6, 2 },
		{ P_GPLL6, 3 },
		{ P_SLEEP_CLK, 6 },
		};

		@@ -1113,7 +1113,7 @@ static struct clk_rcg2 jpeg0_clk_src = {
		};

		static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
		F(24000000, P_GPLL0, 1, 1, 45),
		F(24000000, P_GPLL6, 1, 1, 45),
		F(66670000, P_GPLL0, 12, 0, 0),
		{ }
		};