Commit 9e7b08d2 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/mes12: optimize MES pipe FW version fetching 



Don't fetch it again if we already have it.  It seems the
registers don't reliably have the value at resume in some
cases.

Fixes: 785f0f9f ("drm/amdgpu: Add mes v12_0 ip block support (v4)")
Reviewed-by: default avatarShaoyun.liu <Shaoyun.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent da7dc714

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

+12 −9
Original line number Diff line number Diff line
@@ -1392,6 +1392,8 @@ static int mes_v12_0_queue_init(struct amdgpu_device *adev, 
		mes_v12_0_queue_init_register(ring);

	}



	if (((pipe == AMDGPU_MES_SCHED_PIPE) && !adev->mes.sched_version) ||

	    ((pipe == AMDGPU_MES_KIQ_PIPE) && !adev->mes.kiq_version)) {

		/* get MES scheduler/KIQ versions */

		mutex_lock(&adev->srbm_mutex);

		soc21_grbm_select(adev, 3, pipe, 0, 0);
@@ -1403,6 +1405,7 @@ static int mes_v12_0_queue_init(struct amdgpu_device *adev, 


		soc21_grbm_select(adev, 0, 0, 0, 0);

		mutex_unlock(&adev->srbm_mutex);

	}



	return 0;

}