Loading arch/arm64/boot/dts/apple/s5l8960x-5s.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -8,6 +8,7 @@ #include "s5l8960x.dtsi" #include "s5l8960x-common.dtsi" #include "s5l8960x-opp.dtsi" #include <dt-bindings/input/input.h> / { Loading arch/arm64/boot/dts/apple/s5l8960x-air1.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -8,6 +8,7 @@ #include "s5l8960x.dtsi" #include "s5l8960x-common.dtsi" #include "s5l8965x-opp.dtsi" #include <dt-bindings/input/input.h> / { Loading arch/arm64/boot/dts/apple/s5l8960x-mini2.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -8,6 +8,7 @@ #include "s5l8960x.dtsi" #include "s5l8960x-common.dtsi" #include "s5l8960x-opp.dtsi" #include <dt-bindings/input/input.h> / { Loading arch/arm64/boot/dts/apple/s5l8960x-opp.dtsi 0 → 100644 +45 −0 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0+ OR MIT /* * Operating points for Apple S5L8960X "A7" SoC, Up to 1296 MHz * * target-type: N51, N53, J85, J86. J87, J85m, J86m, J87m * * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> */ / { cyclone_opp: opp-table { compatible = "operating-points-v2"; opp01 { opp-hz = /bits/ 64 <300000000>; opp-level = <1>; clock-latency-ns = <15500>; }; opp02 { opp-hz = /bits/ 64 <396000000>; opp-level = <2>; clock-latency-ns = <43000>; }; opp03 { opp-hz = /bits/ 64 <600000000>; opp-level = <3>; clock-latency-ns = <26000>; }; opp04 { opp-hz = /bits/ 64 <840000000>; opp-level = <4>; clock-latency-ns = <30000>; }; opp05 { opp-hz = /bits/ 64 <1128000000>; opp-level = <5>; clock-latency-ns = <39500>; }; opp06 { opp-hz = /bits/ 64 <1296000000>; opp-level = <6>; clock-latency-ns = <45500>; }; }; }; arch/arm64/boot/dts/apple/s5l8960x.dtsi +10 −0 Original line number Diff line number Diff line Loading @@ -33,6 +33,8 @@ cpu0: cpu@0 { compatible = "apple,cyclone"; reg = <0x0 0x0>; cpu-release-addr = <0 0>; /* To be filled by loader */ operating-points-v2 = <&cyclone_opp>; performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; }; Loading @@ -41,6 +43,8 @@ cpu1: cpu@1 { compatible = "apple,cyclone"; reg = <0x0 0x1>; cpu-release-addr = <0 0>; /* To be filled by loader */ operating-points-v2 = <&cyclone_opp>; performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; }; Loading @@ -53,6 +57,12 @@ soc { nonposted-mmio; ranges; cpufreq: performance-controller@202220000 { compatible = "apple,s5l8960x-cluster-cpufreq"; reg = <0x2 0x02220000 0 0x1000>; #performance-domain-cells = <0>; }; serial0: serial@20a0a0000 { compatible = "apple,s5l-uart"; reg = <0x2 0x0a0a0000 0x0 0x4000>; Loading Loading
arch/arm64/boot/dts/apple/s5l8960x-5s.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -8,6 +8,7 @@ #include "s5l8960x.dtsi" #include "s5l8960x-common.dtsi" #include "s5l8960x-opp.dtsi" #include <dt-bindings/input/input.h> / { Loading
arch/arm64/boot/dts/apple/s5l8960x-air1.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -8,6 +8,7 @@ #include "s5l8960x.dtsi" #include "s5l8960x-common.dtsi" #include "s5l8965x-opp.dtsi" #include <dt-bindings/input/input.h> / { Loading
arch/arm64/boot/dts/apple/s5l8960x-mini2.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -8,6 +8,7 @@ #include "s5l8960x.dtsi" #include "s5l8960x-common.dtsi" #include "s5l8960x-opp.dtsi" #include <dt-bindings/input/input.h> / { Loading
arch/arm64/boot/dts/apple/s5l8960x-opp.dtsi 0 → 100644 +45 −0 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0+ OR MIT /* * Operating points for Apple S5L8960X "A7" SoC, Up to 1296 MHz * * target-type: N51, N53, J85, J86. J87, J85m, J86m, J87m * * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> */ / { cyclone_opp: opp-table { compatible = "operating-points-v2"; opp01 { opp-hz = /bits/ 64 <300000000>; opp-level = <1>; clock-latency-ns = <15500>; }; opp02 { opp-hz = /bits/ 64 <396000000>; opp-level = <2>; clock-latency-ns = <43000>; }; opp03 { opp-hz = /bits/ 64 <600000000>; opp-level = <3>; clock-latency-ns = <26000>; }; opp04 { opp-hz = /bits/ 64 <840000000>; opp-level = <4>; clock-latency-ns = <30000>; }; opp05 { opp-hz = /bits/ 64 <1128000000>; opp-level = <5>; clock-latency-ns = <39500>; }; opp06 { opp-hz = /bits/ 64 <1296000000>; opp-level = <6>; clock-latency-ns = <45500>; }; }; };
arch/arm64/boot/dts/apple/s5l8960x.dtsi +10 −0 Original line number Diff line number Diff line Loading @@ -33,6 +33,8 @@ cpu0: cpu@0 { compatible = "apple,cyclone"; reg = <0x0 0x0>; cpu-release-addr = <0 0>; /* To be filled by loader */ operating-points-v2 = <&cyclone_opp>; performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; }; Loading @@ -41,6 +43,8 @@ cpu1: cpu@1 { compatible = "apple,cyclone"; reg = <0x0 0x1>; cpu-release-addr = <0 0>; /* To be filled by loader */ operating-points-v2 = <&cyclone_opp>; performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; }; Loading @@ -53,6 +57,12 @@ soc { nonposted-mmio; ranges; cpufreq: performance-controller@202220000 { compatible = "apple,s5l8960x-cluster-cpufreq"; reg = <0x2 0x02220000 0 0x1000>; #performance-domain-cells = <0>; }; serial0: serial@20a0a0000 { compatible = "apple,s5l-uart"; reg = <0x2 0x0a0a0000 0x0 0x4000>; Loading