Unverified Commit 9e9397a4 authored by Tero Kristo's avatar Tero Kristo Committed by Ilpo Järvinen
Browse files

platform/x86/intel/tpmi/plr: Add support for the plr mailbox 



Add support for reading fine grained power limit reasons via the PLR
mailbox.

Reviewed-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: default avatarIlpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: default avatarTero Kristo <tero.kristo@linux.intel.com>
Link: https://lore.kernel.org/r/20240527133400.483634-6-tero.kristo@linux.intel.com


Signed-off-by: default avatarIlpo Järvinen <ilpo.jarvinen@linux.intel.com>
parent 811f67c5

drivers/platform/x86/intel/intel_plr_tpmi.c

+153 −4
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 


#include <linux/array_size.h>

#include <linux/auxiliary_bus.h>

#include <linux/bitfield.h>

#include <linux/bitmap.h>

#include <linux/debugfs.h>

#include <linux/device.h>
@@ -14,26 +15,50 @@ 
#include <linux/gfp_types.h>

#include <linux/intel_tpmi.h>

#include <linux/io.h>

#include <linux/iopoll.h>

#include <linux/kstrtox.h>

#include <linux/lockdep.h>

#include <linux/module.h>

#include <linux/mod_devicetable.h>

#include <linux/mutex.h>

#include <linux/seq_file.h>

#include <linux/sprintf.h>

#include <linux/types.h>



#include "tpmi_power_domains.h"



#define PLR_HEADER		0x00

#define PLR_MAILBOX_INTERFACE	0x08

#define PLR_MAILBOX_DATA	0x10

#define PLR_DIE_LEVEL		0x18



#define PLR_MODULE_ID_MASK	GENMASK_ULL(19, 12)

#define PLR_RUN_BUSY		BIT_ULL(63)



#define PLR_COMMAND_WRITE	1



#define PLR_INVALID		GENMASK_ULL(63, 0)



#define PLR_TIMEOUT_US		5

#define PLR_TIMEOUT_MAX_US	1000



#define PLR_COARSE_REASON_BITS	32



struct tpmi_plr;



struct tpmi_plr_die {

	void __iomem *base;

	struct mutex lock; /* Protect access to PLR mailbox */

	int package_id;

	int die_id;

	struct tpmi_plr *plr;

};



struct tpmi_plr {

	struct dentry *dbgfs_dir;

	struct tpmi_plr_die *die_info;

	int num_dies;

	struct auxiliary_device *auxdev;

};



static const char * const plr_coarse_reasons[] = {
@@ -49,6 +74,39 @@ static const char * const plr_coarse_reasons[] = { 
	"DFC",

};



static const char * const plr_fine_reasons[] = {

	"FREQUENCY_CDYN0",

	"FREQUENCY_CDYN1",

	"FREQUENCY_CDYN2",

	"FREQUENCY_CDYN3",

	"FREQUENCY_CDYN4",

	"FREQUENCY_CDYN5",

	"FREQUENCY_FCT",

	"FREQUENCY_PCS_TRL",

	"CURRENT_MTPMAX",

	"POWER_FAST_RAPL",

	"POWER_PKG_PL1_MSR_TPMI",

	"POWER_PKG_PL1_MMIO",

	"POWER_PKG_PL1_PCS",

	"POWER_PKG_PL2_MSR_TPMI",

	"POWER_PKG_PL2_MMIO",

	"POWER_PKG_PL2_PCS",

	"POWER_PLATFORM_PL1_MSR_TPMI",

	"POWER_PLATFORM_PL1_MMIO",

	"POWER_PLATFORM_PL1_PCS",

	"POWER_PLATFORM_PL2_MSR_TPMI",

	"POWER_PLATFORM_PL2_MMIO",

	"POWER_PLATFORM_PL2_PCS",

	"UNKNOWN(22)",

	"THERMAL_PER_CORE",

	"DFC_UFS",

	"PLATFORM_PROCHOT",

	"PLATFORM_HOT_VR",

	"UNKNOWN(27)",

	"UNKNOWN(28)",

	"MISC_PCS_PSTATE",

};



static u64 plr_read(struct tpmi_plr_die *plr_die, int offset)

{

	return readq(plr_die->base + offset);
@@ -59,16 +117,68 @@ static void plr_write(u64 val, struct tpmi_plr_die *plr_die, int offset) 
	writeq(val, plr_die->base + offset);

}



static int plr_read_cpu_status(struct tpmi_plr_die *plr_die, int cpu,

			       u64 *status)

{

	u64 regval;

	int ret;



	lockdep_assert_held(&plr_die->lock);



	regval = FIELD_PREP(PLR_MODULE_ID_MASK, tpmi_get_punit_core_number(cpu));

	regval |= PLR_RUN_BUSY;



	plr_write(regval, plr_die, PLR_MAILBOX_INTERFACE);



	ret = readq_poll_timeout(plr_die->base + PLR_MAILBOX_INTERFACE, regval,

				 !(regval & PLR_RUN_BUSY), PLR_TIMEOUT_US,

				 PLR_TIMEOUT_MAX_US);

	if (ret)

		return ret;



	*status = plr_read(plr_die, PLR_MAILBOX_DATA);



	return 0;

}



static int plr_clear_cpu_status(struct tpmi_plr_die *plr_die, int cpu)

{

	u64 regval;



	lockdep_assert_held(&plr_die->lock);



	regval = FIELD_PREP(PLR_MODULE_ID_MASK, tpmi_get_punit_core_number(cpu));

	regval |= PLR_RUN_BUSY | PLR_COMMAND_WRITE;



	plr_write(0, plr_die, PLR_MAILBOX_DATA);



	plr_write(regval, plr_die, PLR_MAILBOX_INTERFACE);



	return readq_poll_timeout(plr_die->base + PLR_MAILBOX_INTERFACE, regval,

				  !(regval & PLR_RUN_BUSY), PLR_TIMEOUT_US,

				  PLR_TIMEOUT_MAX_US);

}



static void plr_print_bits(struct seq_file *s, u64 val, int bits)

{

	const unsigned long mask[] = { BITMAP_FROM_U64(val) };

	int bit;

	const char *str;

	int bit, index;



	for_each_set_bit(bit, mask, bits) {

		if (bit >= ARRAY_SIZE(plr_coarse_reasons))

			seq_printf(s, " UNKNOWN(%d)", bit);

		if (bit < PLR_COARSE_REASON_BITS) {

			if (bit < ARRAY_SIZE(plr_coarse_reasons))

				str = plr_coarse_reasons[bit];

		} else {

			index = bit - PLR_COARSE_REASON_BITS;

			if (index < ARRAY_SIZE(plr_fine_reasons))

				str = plr_fine_reasons[index];

		}



		if (str)

			seq_printf(s, " %s", str);

		else

			seq_printf(s, " %s", plr_coarse_reasons[bit]);

			seq_printf(s, " UNKNOWN(%d)", bit);

	}



	if (!val)
@@ -80,12 +190,33 @@ static void plr_print_bits(struct seq_file *s, u64 val, int bits) 
static int plr_status_show(struct seq_file *s, void *unused)

{

	struct tpmi_plr_die *plr_die = s->private;

	int ret;

	u64 val;



	val = plr_read(plr_die, PLR_DIE_LEVEL);

	seq_puts(s, "cpus");

	plr_print_bits(s, val, 32);



	guard(mutex)(&plr_die->lock);



	for (int cpu = 0; cpu < nr_cpu_ids; cpu++) {

		if (plr_die->die_id != tpmi_get_power_domain_id(cpu))

			continue;



		if (plr_die->package_id != topology_physical_package_id(cpu))

			continue;



		seq_printf(s, "cpu%d", cpu);

		ret = plr_read_cpu_status(plr_die, cpu, &val);

		if (ret) {

			dev_err(&plr_die->plr->auxdev->dev, "Failed to read PLR for cpu %d, ret=%d\n",

				cpu, ret);

			return ret;

		}



		plr_print_bits(s, val, 64);

	}



	return 0;

}
@@ -106,6 +237,18 @@ static ssize_t plr_status_write(struct file *filp, const char __user *ubuf, 


	plr_write(0, plr_die, PLR_DIE_LEVEL);



	guard(mutex)(&plr_die->lock);



	for (int cpu = 0; cpu < nr_cpu_ids; cpu++) {

		if (plr_die->die_id != tpmi_get_power_domain_id(cpu))

			continue;



		if (plr_die->package_id != topology_physical_package_id(cpu))

			continue;



		plr_clear_cpu_status(plr_die, cpu);

	}



	return count;

}

DEFINE_SHOW_STORE_ATTRIBUTE(plr_status);
@@ -144,6 +287,7 @@ static int intel_plr_probe(struct auxiliary_device *auxdev, const struct auxilia 


	plr->num_dies = num_resources;

	plr->dbgfs_dir = debugfs_create_dir("plr", dentry);

	plr->auxdev = auxdev;



	for (i = 0; i < num_resources; i++) {

		res = tpmi_get_resource_at_index(auxdev, i);
@@ -159,6 +303,10 @@ static int intel_plr_probe(struct auxiliary_device *auxdev, const struct auxilia 
		}



		plr->die_info[i].base = base;

		plr->die_info[i].package_id = plat_info->package_id;

		plr->die_info[i].die_id = i;

		plr->die_info[i].plr = plr;

		mutex_init(&plr->die_info[i].lock);



		if (plr_read(&plr->die_info[i], PLR_HEADER) == PLR_INVALID)

			continue;
@@ -200,5 +348,6 @@ static struct auxiliary_driver intel_plr_aux_driver = { 
module_auxiliary_driver(intel_plr_aux_driver);



MODULE_IMPORT_NS(INTEL_TPMI);

MODULE_IMPORT_NS(INTEL_TPMI_POWER_DOMAIN);

MODULE_DESCRIPTION("Intel TPMI PLR Driver");

MODULE_LICENSE("GPL");