Commit 9ec77e3a authored by Clay King's avatar Clay King Committed by Alex Deucher
Browse files

drm/amd/display: Multiplication result converted to larger type 



Consolidating multiple CodeQL Fixes for alerts with rule id: cpp/integer-multiplication-cast-to-long

Reviewed-by: default avatarJoshua Aberback <joshua.aberback@amd.com>
Signed-off-by: default avatarClay King <clayking@amd.com>
Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: default avatarDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8a359f0f

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

+1 −1
Original line number Diff line number Diff line
@@ -1136,7 +1136,7 @@ static void calculate_bandwidth( 
			}

		}

	}

	data->total_dmifmc_urgent_trips = bw_ceil2(bw_div(data->total_requests_for_adjusted_dmif_size, (bw_add(dceip->dmif_request_buffer_size, bw_int_to_fixed(vbios->number_of_request_slots_gmc_reserves_for_dmif_per_channel * data->number_of_dram_channels)))), bw_int_to_fixed(1));

	data->total_dmifmc_urgent_trips = bw_ceil2(bw_div(data->total_requests_for_adjusted_dmif_size, (bw_add(dceip->dmif_request_buffer_size, bw_int_to_fixed((uint64_t)vbios->number_of_request_slots_gmc_reserves_for_dmif_per_channel * data->number_of_dram_channels)))), bw_int_to_fixed(1));

	data->total_dmifmc_urgent_latency = bw_mul(vbios->dmifmc_urgent_latency, data->total_dmifmc_urgent_trips);

	data->total_display_reads_required_data = bw_int_to_fixed(0);

	data->total_display_reads_required_dram_access_data = bw_int_to_fixed(0);

drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c

+1 −1
Original line number Diff line number Diff line
@@ -284,7 +284,7 @@ struct fixed31_32 dc_fixpt_cos(struct fixed31_32 arg) 
				dc_fixpt_mul(

					square,

					res),

				n * (n - 1)));

				(long long)n * (n - 1)));



		n -= 2;

	} while (n != 0);

drivers/gpu/drm/amd/display/dc/basics/vector.c

+3 −3
Original line number Diff line number Diff line
@@ -170,7 +170,7 @@ bool dal_vector_remove_at_index( 
		memmove(

			vector->container + (index * vector->struct_size),

			vector->container + ((index + 1) * vector->struct_size),

			(vector->count - index - 1) * vector->struct_size);

			(size_t)(vector->count - index - 1) * vector->struct_size);

	vector->count -= 1;



	return true;
@@ -219,7 +219,7 @@ bool dal_vector_insert_at( 
		memmove(

			insert_address + vector->struct_size,

			insert_address,

			vector->struct_size * (vector->count - position));

			(size_t)vector->struct_size * (vector->count - position));



	memmove(

		insert_address,
@@ -271,7 +271,7 @@ struct vector *dal_vector_clone( 


	/* copy vector's data */

	memmove(vec_cloned->container, vector->container,

			vec_cloned->struct_size * vec_cloned->capacity);

			(size_t)vec_cloned->struct_size * vec_cloned->capacity);



	return vec_cloned;

}

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+1 −1
Original line number Diff line number Diff line
@@ -3401,7 +3401,7 @@ bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe) 
		uint32_t height = subvp_active_margin_list.res[i].height;



		refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +

			pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1);

			(uint64_t)pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1);

		refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);

		refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

+1 −1
Original line number Diff line number Diff line
@@ -284,7 +284,7 @@ void mcifwb2_dump_frame(struct mcif_wb *mcif_wb, 


	REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0xf);



	memcpy(dest_luma_buffer,   luma_buffer,   mcif_params->luma_pitch * dest_height);

	memcpy(dest_luma_buffer,   luma_buffer,   (size_t)mcif_params->luma_pitch * dest_height);

	memcpy(dest_chroma_buffer, chroma_buffer, mcif_params->chroma_pitch * dest_height / 2);



	REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0x0);