Commit 9ed335d9 authored by Arunpravin Paneer Selvam's avatar Arunpravin Paneer Selvam Committed by Alex Deucher
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drm/amdgpu: Add mqd for userq compute queue 



Add mqd for userq compute queue for gfx11/gfx12

Signed-off-by: default avatarArunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 31f7efcd

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+4 −0
Original line number Diff line number Diff line
@@ -4312,6 +4312,10 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 


	mqd->cp_hqd_active = prop->hqd_active;



	/* set UQ fenceaddress */

	mqd->fence_address_lo = lower_32_bits(prop->fence_address);

	mqd->fence_address_hi = upper_32_bits(prop->fence_address);



	return 0;

}

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

+4 −0
Original line number Diff line number Diff line
@@ -3215,6 +3215,10 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 


	mqd->cp_hqd_active = prop->hqd_active;



	/* set UQ fenceaddress */

	mqd->fence_address_lo = lower_32_bits(prop->fence_address);

	mqd->fence_address_hi = upper_32_bits(prop->fence_address);



	return 0;

}

drivers/gpu/drm/amd/include/v11_structs.h

+2 −2
Original line number Diff line number Diff line
@@ -1118,8 +1118,8 @@ struct v11_compute_mqd { 
	uint32_t reserved_443; // offset: 443  (0x1BB)

	uint32_t reserved_444; // offset: 444  (0x1BC)

	uint32_t reserved_445; // offset: 445  (0x1BD)

	uint32_t reserved_446; // offset: 446  (0x1BE)

	uint32_t reserved_447; // offset: 447  (0x1BF)

	uint32_t fence_address_lo; // offset: 446  (0x1BE)

	uint32_t fence_address_hi; // offset: 447  (0x1BF)

	uint32_t gws_0_val; // offset: 448  (0x1C0)

	uint32_t gws_1_val; // offset: 449  (0x1C1)

	uint32_t gws_2_val; // offset: 450  (0x1C2)

drivers/gpu/drm/amd/include/v12_structs.h

+2 −2
Original line number Diff line number Diff line
@@ -1118,8 +1118,8 @@ struct v12_compute_mqd { 
    uint32_t reserved_443; // offset: 443  (0x1BB)

    uint32_t reserved_444; // offset: 444  (0x1BC)

    uint32_t reserved_445; // offset: 445  (0x1BD)

    uint32_t reserved_446; // offset: 446  (0x1BE)

    uint32_t reserved_447; // offset: 447  (0x1BF)

    uint32_t fence_address_lo; // offset: 446  (0x1BE)

    uint32_t fence_address_hi; // offset: 447  (0x1BF)

    uint32_t gws_0_val; // offset: 448  (0x1C0)

    uint32_t gws_1_val; // offset: 449  (0x1C1)

    uint32_t gws_2_val; // offset: 450  (0x1C2)