Unverified Commit 9eeeb2a7 authored by Xi Pardee's avatar Xi Pardee Committed by Ilpo Järvinen
Browse files

platform/x86/intel/pmc: Remove unnecessary declarations in header 



Remove unnecessary declarations in header file. Variable that are
used by only one .c file are removed from header file and changed
to be static in their corresponding .c file.

Signed-off-by: default avatarXi Pardee <xi.pardee@linux.intel.com>
Link: https://lore.kernel.org/r/20250214214416.10150-3-xi.pardee@linux.intel.com


Reviewed-by: default avatarIlpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: default avatarIlpo Järvinen <ilpo.jarvinen@linux.intel.com>
parent d31feed7

drivers/platform/x86/intel/pmc/adl.c

+17 −17
Original line number Diff line number Diff line
@@ -11,7 +11,7 @@ 
#include "core.h"



/* Alder Lake: PGD PFET Enable Ack Status Register(s) bitmap */

const struct pmc_bit_map adl_pfear_map[] = {

static const struct pmc_bit_map adl_pfear_map[] = {

	{"SPI/eSPI",		BIT(2)},

	{"XHCI",		BIT(3)},

	{"SPA",			BIT(4)},
@@ -54,7 +54,7 @@ const struct pmc_bit_map adl_pfear_map[] = { 
	{}

};



const struct pmc_bit_map *ext_adl_pfear_map[] = {

static const struct pmc_bit_map *ext_adl_pfear_map[] = {

	/*

	 * Check intel_pmc_core_ids[] users of cnp_reg_map for

	 * a list of core SoCs using this.
@@ -63,7 +63,7 @@ const struct pmc_bit_map *ext_adl_pfear_map[] = { 
	NULL

};



const struct pmc_bit_map adl_ltr_show_map[] = {

static const struct pmc_bit_map adl_ltr_show_map[] = {

	{"SOUTHPORT_A",		CNP_PMC_LTR_SPA},

	{"SOUTHPORT_B",		CNP_PMC_LTR_SPB},

	{"SATA",		CNP_PMC_LTR_SATA},
@@ -100,7 +100,7 @@ const struct pmc_bit_map adl_ltr_show_map[] = { 
	{}

};



const struct pmc_bit_map adl_clocksource_status_map[] = {

static const struct pmc_bit_map adl_clocksource_status_map[] = {

	{"CLKPART1_OFF_STS",			BIT(0)},

	{"CLKPART2_OFF_STS",			BIT(1)},

	{"CLKPART3_OFF_STS",			BIT(2)},
@@ -128,7 +128,7 @@ const struct pmc_bit_map adl_clocksource_status_map[] = { 
	{}

};



const struct pmc_bit_map adl_power_gating_status_0_map[] = {

static const struct pmc_bit_map adl_power_gating_status_0_map[] = {

	{"PMC_PGD0_PG_STS",			BIT(0)},

	{"DMI_PGD0_PG_STS",			BIT(1)},

	{"ESPISPI_PGD0_PG_STS",			BIT(2)},
@@ -158,7 +158,7 @@ const struct pmc_bit_map adl_power_gating_status_0_map[] = { 
	{}

};



const struct pmc_bit_map adl_power_gating_status_1_map[] = {

static const struct pmc_bit_map adl_power_gating_status_1_map[] = {

	{"USBR0_PGD0_PG_STS",			BIT(0)},

	{"SMT1_PGD0_PG_STS",			BIT(2)},

	{"CSMERTC_PGD0_PG_STS",			BIT(6)},
@@ -170,14 +170,14 @@ const struct pmc_bit_map adl_power_gating_status_1_map[] = { 
	{}

};



const struct pmc_bit_map adl_power_gating_status_2_map[] = {

static const struct pmc_bit_map adl_power_gating_status_2_map[] = {

	{"THC0_PGD0_PG_STS",			BIT(7)},

	{"THC1_PGD0_PG_STS",			BIT(8)},

	{"SPF_PGD0_PG_STS",			BIT(14)},

	{}

};



const struct pmc_bit_map adl_d3_status_0_map[] = {

static const struct pmc_bit_map adl_d3_status_0_map[] = {

	{"ISH_D3_STS",				BIT(2)},

	{"LPSS_D3_STS",				BIT(3)},

	{"XDCI_D3_STS",				BIT(4)},
@@ -193,13 +193,13 @@ const struct pmc_bit_map adl_d3_status_0_map[] = { 
	{}

};



const struct pmc_bit_map adl_d3_status_1_map[] = {

static const struct pmc_bit_map adl_d3_status_1_map[] = {

	{"GBE_D3_STS",				BIT(19)},

	{"CNVI_D3_STS",				BIT(27)},

	{}

};



const struct pmc_bit_map adl_d3_status_2_map[] = {

static const struct pmc_bit_map adl_d3_status_2_map[] = {

	{"CSMERTC_D3_STS",			BIT(1)},

	{"CSE_D3_STS",				BIT(4)},

	{"KVMCC_D3_STS",			BIT(5)},
@@ -210,20 +210,20 @@ const struct pmc_bit_map adl_d3_status_2_map[] = { 
	{}

};



const struct pmc_bit_map adl_d3_status_3_map[] = {

static const struct pmc_bit_map adl_d3_status_3_map[] = {

	{"THC0_D3_STS",				BIT(14)},

	{"THC1_D3_STS",				BIT(15)},

	{}

};



const struct pmc_bit_map adl_vnn_req_status_0_map[] = {

static const struct pmc_bit_map adl_vnn_req_status_0_map[] = {

	{"ISH_VNN_REQ_STS",			BIT(2)},

	{"ESPISPI_VNN_REQ_STS",			BIT(18)},

	{"DSP_VNN_REQ_STS",			BIT(19)},

	{}

};



const struct pmc_bit_map adl_vnn_req_status_1_map[] = {

static const struct pmc_bit_map adl_vnn_req_status_1_map[] = {

	{"NPK_VNN_REQ_STS",			BIT(4)},

	{"EXI_VNN_REQ_STS",			BIT(9)},

	{"GBE_VNN_REQ_STS",			BIT(19)},
@@ -232,7 +232,7 @@ const struct pmc_bit_map adl_vnn_req_status_1_map[] = { 
	{}

};



const struct pmc_bit_map adl_vnn_req_status_2_map[] = {

static const struct pmc_bit_map adl_vnn_req_status_2_map[] = {

	{"CSMERTC_VNN_REQ_STS",			BIT(1)},

	{"CSE_VNN_REQ_STS",			BIT(4)},

	{"SMT1_VNN_REQ_STS",			BIT(8)},
@@ -245,12 +245,12 @@ const struct pmc_bit_map adl_vnn_req_status_2_map[] = { 
	{}

};



const struct pmc_bit_map adl_vnn_req_status_3_map[] = {

static const struct pmc_bit_map adl_vnn_req_status_3_map[] = {

	{"GPIOCOM5_VNN_REQ_STS",		BIT(11)},

	{}

};



const struct pmc_bit_map adl_vnn_misc_status_map[] = {

static const struct pmc_bit_map adl_vnn_misc_status_map[] = {

	{"CPU_C10_REQ_STS",			BIT(0)},

	{"PCIe_LPM_En_REQ_STS",			BIT(3)},

	{"ITH_REQ_STS",				BIT(5)},
@@ -265,7 +265,7 @@ const struct pmc_bit_map adl_vnn_misc_status_map[] = { 
	{}

};



const struct pmc_bit_map *adl_lpm_maps[] = {

static const struct pmc_bit_map *adl_lpm_maps[] = {

	adl_clocksource_status_map,

	adl_power_gating_status_0_map,

	adl_power_gating_status_1_map,

drivers/platform/x86/intel/pmc/arl.c

+29 −29
Original line number Diff line number Diff line
@@ -20,7 +20,7 @@ 


static const u8 ARL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20};



const struct pmc_bit_map arl_socs_ltr_show_map[] = {

static const struct pmc_bit_map arl_socs_ltr_show_map[] = {

	{"SOUTHPORT_A",		CNP_PMC_LTR_SPA},

	{"SOUTHPORT_B",		CNP_PMC_LTR_SPB},

	{"SATA",		CNP_PMC_LTR_SATA},
@@ -60,7 +60,7 @@ const struct pmc_bit_map arl_socs_ltr_show_map[] = { 
	{}

};



const struct pmc_bit_map arl_socs_clocksource_status_map[] = {

static const struct pmc_bit_map arl_socs_clocksource_status_map[] = {

	{"AON2_OFF_STS",		BIT(0)},

	{"AON3_OFF_STS",		BIT(1)},

	{"AON4_OFF_STS",		BIT(2)},
@@ -88,7 +88,7 @@ const struct pmc_bit_map arl_socs_clocksource_status_map[] = { 
	{}

};



const struct pmc_bit_map arl_socs_power_gating_status_0_map[] = {

static const struct pmc_bit_map arl_socs_power_gating_status_0_map[] = {

	{"PMC_PGD0_PG_STS",		BIT(0)},

	{"DMI_PGD0_PG_STS",		BIT(1)},

	{"ESPISPI_PGD0_PG_STS",		BIT(2)},
@@ -124,7 +124,7 @@ const struct pmc_bit_map arl_socs_power_gating_status_0_map[] = { 
	{}

};



const struct pmc_bit_map arl_socs_power_gating_status_1_map[] = {

static const struct pmc_bit_map arl_socs_power_gating_status_1_map[] = {

	{"USBR0_PGD0_PG_STS",		BIT(0)},

	{"SUSRAM_PGD0_PG_STS",		BIT(1)},

	{"SMT1_PGD0_PG_STS",		BIT(2)},
@@ -160,7 +160,7 @@ const struct pmc_bit_map arl_socs_power_gating_status_1_map[] = { 
	{}

};



const struct pmc_bit_map arl_socs_power_gating_status_2_map[] = {

static const struct pmc_bit_map arl_socs_power_gating_status_2_map[] = {

	{"PSF8_PGD0_PG_STS",		BIT(0)},

	{"FIA_PGD0_PG_STS",		BIT(1)},

	{"SOC_D2D_PGD3_PG_STS",		BIT(2)},
@@ -188,7 +188,7 @@ const struct pmc_bit_map arl_socs_power_gating_status_2_map[] = { 
	{}

};



const struct pmc_bit_map arl_socs_d3_status_2_map[] = {

static const struct pmc_bit_map arl_socs_d3_status_2_map[] = {

	{"CSMERTC_D3_STS",		BIT(1)},

	{"SUSRAM_D3_STS",		BIT(2)},

	{"CSE_D3_STS",			BIT(4)},
@@ -207,7 +207,7 @@ const struct pmc_bit_map arl_socs_d3_status_2_map[] = { 
	{}

};



const struct pmc_bit_map arl_socs_d3_status_3_map[] = {

static const struct pmc_bit_map arl_socs_d3_status_3_map[] = {

	{"GBETSN_D3_STS",		BIT(13)},

	{"THC0_D3_STS",			BIT(14)},

	{"THC1_D3_STS",			BIT(15)},
@@ -215,13 +215,13 @@ const struct pmc_bit_map arl_socs_d3_status_3_map[] = { 
	{}

};



const struct pmc_bit_map arl_socs_vnn_req_status_3_map[] = {

static const struct pmc_bit_map arl_socs_vnn_req_status_3_map[] = {

	{"DTS0_VNN_REQ_STS",		BIT(7)},

	{"GPIOCOM5_VNN_REQ_STS",	BIT(11)},

	{}

};



const struct pmc_bit_map *arl_socs_lpm_maps[] = {

static const struct pmc_bit_map *arl_socs_lpm_maps[] = {

	arl_socs_clocksource_status_map,

	arl_socs_power_gating_status_0_map,

	arl_socs_power_gating_status_1_map,
@@ -239,7 +239,7 @@ const struct pmc_bit_map *arl_socs_lpm_maps[] = { 
	NULL

};



const struct pmc_bit_map arl_socs_pfear_map[] = {

static const struct pmc_bit_map arl_socs_pfear_map[] = {

	{"RSVD64",			BIT(0)},

	{"RSVD65",			BIT(1)},

	{"RSVD66",			BIT(2)},
@@ -250,13 +250,13 @@ const struct pmc_bit_map arl_socs_pfear_map[] = { 
	{}

};



const struct pmc_bit_map *ext_arl_socs_pfear_map[] = {

static const struct pmc_bit_map *ext_arl_socs_pfear_map[] = {

	mtl_socm_pfear_map,

	arl_socs_pfear_map,

	NULL

};



const struct pmc_reg_map arl_socs_reg_map = {

static const struct pmc_reg_map arl_socs_reg_map = {

	.pfear_sts = ext_arl_socs_pfear_map,

	.ppfear_buckets = ARL_SOCS_PPFEAR_NUM_ENTRIES,

	.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
@@ -284,7 +284,7 @@ const struct pmc_reg_map arl_socs_reg_map = { 
	.pson_residency_counter_step = TGL_PSON_RES_COUNTER_STEP,

};



const struct pmc_bit_map arl_pchs_ltr_show_map[] = {

static const struct pmc_bit_map arl_pchs_ltr_show_map[] = {

	{"SOUTHPORT_A",		CNP_PMC_LTR_SPA},

	{"SOUTHPORT_B",		CNP_PMC_LTR_SPB},

	{"SATA",		CNP_PMC_LTR_SATA},
@@ -324,7 +324,7 @@ const struct pmc_bit_map arl_pchs_ltr_show_map[] = { 
	{}

};



const struct pmc_bit_map arl_pchs_clocksource_status_map[] = {

static const struct pmc_bit_map arl_pchs_clocksource_status_map[] = {

	{"AON2_OFF_STS",		BIT(0)},

	{"AON3_OFF_STS",		BIT(1)},

	{"AON4_OFF_STS",		BIT(2)},
@@ -359,7 +359,7 @@ const struct pmc_bit_map arl_pchs_clocksource_status_map[] = { 
	{}

};



const struct pmc_bit_map arl_pchs_power_gating_status_0_map[] = {

static const struct pmc_bit_map arl_pchs_power_gating_status_0_map[] = {

	{"PMC_PGD0_PG_STS",		BIT(0)},

	{"DMI_PGD0_PG_STS",		BIT(1)},

	{"ESPISPI_PGD0_PG_STS",		BIT(2)},
@@ -395,7 +395,7 @@ const struct pmc_bit_map arl_pchs_power_gating_status_0_map[] = { 
	{}

};



const struct pmc_bit_map arl_pchs_power_gating_status_1_map[] = {

static const struct pmc_bit_map arl_pchs_power_gating_status_1_map[] = {

	{"USBR0_PGD0_PG_STS",		BIT(0)},

	{"SUSRAM_PGD0_PG_STS",		BIT(1)},

	{"SMT1_PGD0_PG_STS",		BIT(2)},
@@ -431,7 +431,7 @@ const struct pmc_bit_map arl_pchs_power_gating_status_1_map[] = { 
	{}

};



const struct pmc_bit_map arl_pchs_power_gating_status_2_map[] = {

static const struct pmc_bit_map arl_pchs_power_gating_status_2_map[] = {

	{"U3FPW2_PGD0_PG_STS",		BIT(0)},

	{"FIA_PGD0_PG_STS",		BIT(1)},

	{"FIACPCB_X_PGD0_PG_STS",	BIT(2)},
@@ -458,7 +458,7 @@ const struct pmc_bit_map arl_pchs_power_gating_status_2_map[] = { 
	{}

};



const struct pmc_bit_map arl_pchs_d3_status_0_map[] = {

static const struct pmc_bit_map arl_pchs_d3_status_0_map[] = {

	{"SPF_D3_STS",			BIT(0)},

	{"LPSS_D3_STS",			BIT(3)},

	{"XDCI_D3_STS",			BIT(4)},
@@ -475,7 +475,7 @@ const struct pmc_bit_map arl_pchs_d3_status_0_map[] = { 
	{}

};



const struct pmc_bit_map arl_pchs_d3_status_1_map[] = {

static const struct pmc_bit_map arl_pchs_d3_status_1_map[] = {

	{"GBETSN1_D3_STS",		BIT(14)},

	{"GBE_D3_STS",			BIT(19)},

	{"ITSS_D3_STS",			BIT(23)},
@@ -484,7 +484,7 @@ const struct pmc_bit_map arl_pchs_d3_status_1_map[] = { 
	{}

};



const struct pmc_bit_map arl_pchs_d3_status_2_map[] = {

static const struct pmc_bit_map arl_pchs_d3_status_2_map[] = {

	{"CSMERTC_D3_STS",		BIT(1)},

	{"SUSRAM_D3_STS",		BIT(2)},

	{"CSE_D3_STS",			BIT(4)},
@@ -505,7 +505,7 @@ const struct pmc_bit_map arl_pchs_d3_status_2_map[] = { 
	{}

};



const struct pmc_bit_map arl_pchs_d3_status_3_map[] = {

static const struct pmc_bit_map arl_pchs_d3_status_3_map[] = {

	{"ESE_D3_STS",			BIT(3)},

	{"GBETSN_D3_STS",		BIT(13)},

	{"THC0_D3_STS",			BIT(14)},
@@ -514,13 +514,13 @@ const struct pmc_bit_map arl_pchs_d3_status_3_map[] = { 
	{}

};



const struct pmc_bit_map arl_pchs_vnn_req_status_0_map[] = {

static const struct pmc_bit_map arl_pchs_vnn_req_status_0_map[] = {

	{"FIA_VNN_REQ_STS",		BIT(17)},

	{"ESPISPI_VNN_REQ_STS",		BIT(18)},

	{}

};



const struct pmc_bit_map arl_pchs_vnn_req_status_1_map[] = {

static const struct pmc_bit_map arl_pchs_vnn_req_status_1_map[] = {

	{"NPK_VNN_REQ_STS",		BIT(4)},

	{"DFXAGG_VNN_REQ_STS",		BIT(8)},

	{"EXI_VNN_REQ_STS",		BIT(9)},
@@ -531,7 +531,7 @@ const struct pmc_bit_map arl_pchs_vnn_req_status_1_map[] = { 
	{}

};



const struct pmc_bit_map arl_pchs_vnn_req_status_2_map[] = {

static const struct pmc_bit_map arl_pchs_vnn_req_status_2_map[] = {

	{"FIA2_VNN_REQ_STS",		BIT(0)},

	{"CSMERTC_VNN_REQ_STS",		BIT(1)},

	{"CSE_VNN_REQ_STS",		BIT(4)},
@@ -549,7 +549,7 @@ const struct pmc_bit_map arl_pchs_vnn_req_status_2_map[] = { 
	{}

};



const struct pmc_bit_map arl_pchs_vnn_req_status_3_map[] = {

static const struct pmc_bit_map arl_pchs_vnn_req_status_3_map[] = {

	{"ESE_VNN_REQ_STS",		BIT(3)},

	{"DTS0_VNN_REQ_STS",		BIT(7)},

	{"GPIOCOM5_VNN_REQ_STS",	BIT(11)},
@@ -557,7 +557,7 @@ const struct pmc_bit_map arl_pchs_vnn_req_status_3_map[] = { 
	{}

};



const struct pmc_bit_map arl_pchs_vnn_misc_status_map[] = {

static const struct pmc_bit_map arl_pchs_vnn_misc_status_map[] = {

	{"CPU_C10_REQ_STS",			BIT(0)},

	{"TS_OFF_REQ_STS",			BIT(1)},

	{"PNDE_MET_REQ_STS",			BIT(2)},
@@ -587,7 +587,7 @@ const struct pmc_bit_map arl_pchs_vnn_misc_status_map[] = { 
	{}

};



const struct pmc_bit_map arl_pchs_signal_status_map[] = {

static const struct pmc_bit_map arl_pchs_signal_status_map[] = {

	{"LSX_Wake0_STS",		BIT(0)},

	{"LSX_Wake1_STS",		BIT(1)},

	{"LSX_Wake2_STS",		BIT(2)},
@@ -607,7 +607,7 @@ const struct pmc_bit_map arl_pchs_signal_status_map[] = { 
	{}

};



const struct pmc_bit_map *arl_pchs_lpm_maps[] = {

static const struct pmc_bit_map *arl_pchs_lpm_maps[] = {

	arl_pchs_clocksource_status_map,

	arl_pchs_power_gating_status_0_map,

	arl_pchs_power_gating_status_1_map,
@@ -625,7 +625,7 @@ const struct pmc_bit_map *arl_pchs_lpm_maps[] = { 
	NULL

};



const struct pmc_reg_map arl_pchs_reg_map = {

static const struct pmc_reg_map arl_pchs_reg_map = {

	.pfear_sts = ext_arl_socs_pfear_map,

	.ppfear_buckets = ARL_SOCS_PPFEAR_NUM_ENTRIES,

	.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,

drivers/platform/x86/intel/pmc/cnp.c

+4 −4
Original line number Diff line number Diff line
@@ -88,7 +88,7 @@ const struct pmc_bit_map cnp_pfear_map[] = { 
	{}

};



const struct pmc_bit_map *ext_cnp_pfear_map[] = {

static const struct pmc_bit_map *ext_cnp_pfear_map[] = {

	/*

	 * Check intel_pmc_core_ids[] users of cnp_reg_map for

	 * a list of core SoCs using this.
@@ -97,7 +97,7 @@ const struct pmc_bit_map *ext_cnp_pfear_map[] = { 
	NULL

};



const struct pmc_bit_map cnp_slps0_dbg0_map[] = {

static const struct pmc_bit_map cnp_slps0_dbg0_map[] = {

	{"AUDIO_D3",		BIT(0)},

	{"OTG_D3",		BIT(1)},

	{"XHCI_D3",		BIT(2)},
@@ -110,7 +110,7 @@ const struct pmc_bit_map cnp_slps0_dbg0_map[] = { 
	{}

};



const struct pmc_bit_map cnp_slps0_dbg1_map[] = {

static const struct pmc_bit_map cnp_slps0_dbg1_map[] = {

	{"SDIO_PLL_OFF",	BIT(0)},

	{"USB2_PLL_OFF",	BIT(1)},

	{"AUDIO_PLL_OFF",	BIT(2)},
@@ -127,7 +127,7 @@ const struct pmc_bit_map cnp_slps0_dbg1_map[] = { 
	{}

};



const struct pmc_bit_map cnp_slps0_dbg2_map[] = {

static const struct pmc_bit_map cnp_slps0_dbg2_map[] = {

	{"MPHY_CORE_GATED",	BIT(0)},

	{"CSME_GATED",		BIT(1)},

	{"USB2_SUS_GATED",	BIT(2)},

drivers/platform/x86/intel/pmc/core.h

+0 −126
Original line number Diff line number Diff line
@@ -467,148 +467,22 @@ struct pmc_dev_info { 
};



extern const struct pmc_bit_map msr_map[];

extern const struct pmc_bit_map spt_pll_map[];

extern const struct pmc_bit_map spt_mphy_map[];

extern const struct pmc_bit_map spt_pfear_map[];

extern const struct pmc_bit_map *ext_spt_pfear_map[];

extern const struct pmc_bit_map spt_ltr_show_map[];

extern const struct pmc_reg_map spt_reg_map;

extern const struct pmc_bit_map cnp_pfear_map[];

extern const struct pmc_bit_map *ext_cnp_pfear_map[];

extern const struct pmc_bit_map cnp_slps0_dbg0_map[];

extern const struct pmc_bit_map cnp_slps0_dbg1_map[];

extern const struct pmc_bit_map cnp_slps0_dbg2_map[];

extern const struct pmc_bit_map *cnp_slps0_dbg_maps[];

extern const struct pmc_bit_map cnp_ltr_show_map[];

extern const struct pmc_reg_map cnp_reg_map;

extern const struct pmc_bit_map icl_pfear_map[];

extern const struct pmc_bit_map *ext_icl_pfear_map[];

extern const struct pmc_reg_map icl_reg_map;

extern const struct pmc_bit_map tgl_pfear_map[];

extern const struct pmc_bit_map *ext_tgl_pfear_map[];

extern const struct pmc_bit_map tgl_clocksource_status_map[];

extern const struct pmc_bit_map tgl_power_gating_status_map[];

extern const struct pmc_bit_map tgl_d3_status_map[];

extern const struct pmc_bit_map tgl_vnn_req_status_map[];

extern const struct pmc_bit_map tgl_vnn_misc_status_map[];

extern const struct pmc_bit_map tgl_signal_status_map[];

extern const struct pmc_bit_map *tgl_lpm_maps[];

extern const struct pmc_reg_map tgl_reg_map;

extern const struct pmc_reg_map tgl_h_reg_map;

extern const struct pmc_bit_map adl_pfear_map[];

extern const struct pmc_bit_map *ext_adl_pfear_map[];

extern const struct pmc_bit_map adl_ltr_show_map[];

extern const struct pmc_bit_map adl_clocksource_status_map[];

extern const struct pmc_bit_map adl_power_gating_status_0_map[];

extern const struct pmc_bit_map adl_power_gating_status_1_map[];

extern const struct pmc_bit_map adl_power_gating_status_2_map[];

extern const struct pmc_bit_map adl_d3_status_0_map[];

extern const struct pmc_bit_map adl_d3_status_1_map[];

extern const struct pmc_bit_map adl_d3_status_2_map[];

extern const struct pmc_bit_map adl_d3_status_3_map[];

extern const struct pmc_bit_map adl_vnn_req_status_0_map[];

extern const struct pmc_bit_map adl_vnn_req_status_1_map[];

extern const struct pmc_bit_map adl_vnn_req_status_2_map[];

extern const struct pmc_bit_map adl_vnn_req_status_3_map[];

extern const struct pmc_bit_map adl_vnn_misc_status_map[];

extern const struct pmc_bit_map *adl_lpm_maps[];

extern const struct pmc_reg_map adl_reg_map;

extern const struct pmc_bit_map mtl_socm_pfear_map[];

extern const struct pmc_bit_map *ext_mtl_socm_pfear_map[];

extern const struct pmc_bit_map mtl_socm_ltr_show_map[];

extern const struct pmc_bit_map mtl_socm_clocksource_status_map[];

extern const struct pmc_bit_map mtl_socm_power_gating_status_0_map[];

extern const struct pmc_bit_map mtl_socm_power_gating_status_1_map[];

extern const struct pmc_bit_map mtl_socm_power_gating_status_2_map[];

extern const struct pmc_bit_map mtl_socm_d3_status_0_map[];

extern const struct pmc_bit_map mtl_socm_d3_status_1_map[];

extern const struct pmc_bit_map mtl_socm_d3_status_2_map[];

extern const struct pmc_bit_map mtl_socm_d3_status_3_map[];

extern const struct pmc_bit_map mtl_socm_vnn_req_status_0_map[];

extern const struct pmc_bit_map mtl_socm_vnn_req_status_1_map[];

extern const struct pmc_bit_map mtl_socm_vnn_req_status_2_map[];

extern const struct pmc_bit_map mtl_socm_vnn_req_status_3_map[];

extern const struct pmc_bit_map mtl_socm_vnn_misc_status_map[];

extern const struct pmc_bit_map mtl_socm_signal_status_map[];

extern const struct pmc_bit_map *mtl_socm_lpm_maps[];

extern const struct pmc_reg_map mtl_socm_reg_map;

extern const struct pmc_bit_map mtl_ioep_pfear_map[];

extern const struct pmc_bit_map *ext_mtl_ioep_pfear_map[];

extern const struct pmc_bit_map mtl_ioep_ltr_show_map[];

extern const struct pmc_bit_map mtl_ioep_clocksource_status_map[];

extern const struct pmc_bit_map mtl_ioep_power_gating_status_0_map[];

extern const struct pmc_bit_map mtl_ioep_power_gating_status_1_map[];

extern const struct pmc_bit_map mtl_ioep_power_gating_status_2_map[];

extern const struct pmc_bit_map mtl_ioep_d3_status_0_map[];

extern const struct pmc_bit_map mtl_ioep_d3_status_1_map[];

extern const struct pmc_bit_map mtl_ioep_d3_status_2_map[];

extern const struct pmc_bit_map mtl_ioep_d3_status_3_map[];

extern const struct pmc_bit_map mtl_ioep_vnn_req_status_0_map[];

extern const struct pmc_bit_map mtl_ioep_vnn_req_status_1_map[];

extern const struct pmc_bit_map mtl_ioep_vnn_req_status_2_map[];

extern const struct pmc_bit_map mtl_ioep_vnn_req_status_3_map[];

extern const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[];

extern const struct pmc_bit_map *mtl_ioep_lpm_maps[];

extern const struct pmc_reg_map mtl_ioep_reg_map;

extern const struct pmc_bit_map mtl_ioem_pfear_map[];

extern const struct pmc_bit_map *ext_mtl_ioem_pfear_map[];

extern const struct pmc_bit_map mtl_ioem_power_gating_status_1_map[];

extern const struct pmc_bit_map mtl_ioem_vnn_req_status_1_map[];

extern const struct pmc_bit_map *mtl_ioem_lpm_maps[];

extern const struct pmc_reg_map mtl_ioem_reg_map;

extern const struct pmc_reg_map lnl_socm_reg_map;



/* LNL */

extern const struct pmc_bit_map lnl_ltr_show_map[];

extern const struct pmc_bit_map lnl_clocksource_status_map[];

extern const struct pmc_bit_map lnl_power_gating_status_0_map[];

extern const struct pmc_bit_map lnl_power_gating_status_1_map[];

extern const struct pmc_bit_map lnl_power_gating_status_2_map[];

extern const struct pmc_bit_map lnl_d3_status_0_map[];

extern const struct pmc_bit_map lnl_d3_status_1_map[];

extern const struct pmc_bit_map lnl_d3_status_2_map[];

extern const struct pmc_bit_map lnl_d3_status_3_map[];

extern const struct pmc_bit_map lnl_vnn_req_status_0_map[];

extern const struct pmc_bit_map lnl_vnn_req_status_1_map[];

extern const struct pmc_bit_map lnl_vnn_req_status_2_map[];

extern const struct pmc_bit_map lnl_vnn_req_status_3_map[];

extern const struct pmc_bit_map lnl_vnn_misc_status_map[];

extern const struct pmc_bit_map *lnl_lpm_maps[];

extern const struct pmc_bit_map *lnl_blk_maps[];

extern const struct pmc_bit_map lnl_pfear_map[];

extern const struct pmc_bit_map *ext_lnl_pfear_map[];

extern const struct pmc_bit_map lnl_signal_status_map[];



/* ARL */

extern const struct pmc_bit_map arl_socs_ltr_show_map[];

extern const struct pmc_bit_map arl_socs_clocksource_status_map[];

extern const struct pmc_bit_map arl_socs_power_gating_status_0_map[];

extern const struct pmc_bit_map arl_socs_power_gating_status_1_map[];

extern const struct pmc_bit_map arl_socs_power_gating_status_2_map[];

extern const struct pmc_bit_map arl_socs_d3_status_2_map[];

extern const struct pmc_bit_map arl_socs_d3_status_3_map[];

extern const struct pmc_bit_map arl_socs_vnn_req_status_3_map[];

extern const struct pmc_bit_map *arl_socs_lpm_maps[];

extern const struct pmc_bit_map arl_socs_pfear_map[];

extern const struct pmc_bit_map *ext_arl_socs_pfear_map[];

extern const struct pmc_reg_map arl_socs_reg_map;

extern const struct pmc_bit_map arl_pchs_ltr_show_map[];

extern const struct pmc_bit_map arl_pchs_clocksource_status_map[];

extern const struct pmc_bit_map arl_pchs_power_gating_status_0_map[];

extern const struct pmc_bit_map arl_pchs_power_gating_status_1_map[];

extern const struct pmc_bit_map arl_pchs_power_gating_status_2_map[];

extern const struct pmc_bit_map arl_pchs_d3_status_0_map[];

extern const struct pmc_bit_map arl_pchs_d3_status_1_map[];

extern const struct pmc_bit_map arl_pchs_d3_status_2_map[];

extern const struct pmc_bit_map arl_pchs_d3_status_3_map[];

extern const struct pmc_bit_map arl_pchs_vnn_req_status_0_map[];

extern const struct pmc_bit_map arl_pchs_vnn_req_status_1_map[];

extern const struct pmc_bit_map arl_pchs_vnn_req_status_2_map[];

extern const struct pmc_bit_map arl_pchs_vnn_req_status_3_map[];

extern const struct pmc_bit_map arl_pchs_vnn_misc_status_map[];

extern const struct pmc_bit_map arl_pchs_signal_status_map[];

extern const struct pmc_bit_map *arl_pchs_lpm_maps[];

extern const struct pmc_reg_map arl_pchs_reg_map;



extern void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev);

extern int pmc_core_ssram_get_lpm_reqs(struct pmc_dev *pmcdev);

drivers/platform/x86/intel/pmc/icl.c

+3 −3
Original line number Diff line number Diff line
@@ -10,7 +10,7 @@ 


#include "core.h"



const struct pmc_bit_map icl_pfear_map[] = {

static const struct pmc_bit_map icl_pfear_map[] = {

	{"RES_65",		BIT(0)},

	{"RES_66",		BIT(1)},

	{"RES_67",		BIT(2)},
@@ -22,7 +22,7 @@ const struct pmc_bit_map icl_pfear_map[] = { 
	{}

};



const struct pmc_bit_map *ext_icl_pfear_map[] = {

static const struct pmc_bit_map *ext_icl_pfear_map[] = {

	/*

	 * Check intel_pmc_core_ids[] users of icl_reg_map for

	 * a list of core SoCs using this.
@@ -32,7 +32,7 @@ const struct pmc_bit_map *ext_icl_pfear_map[] = { 
	NULL

};



const struct pmc_reg_map icl_reg_map = {

static const struct pmc_reg_map icl_reg_map = {

	.pfear_sts = ext_icl_pfear_map,

	.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,

	.slp_s0_res_counter_step = ICL_PMC_SLP_S0_RES_COUNTER_STEP,