Commit 9f18b55b authored by Himal Prasad Ghimiray's avatar Himal Prasad Ghimiray Committed by Matt Roper
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drm/xe/xe2: Add workaround 18033852989 



This workaround applies to RCS engine's context, hence added as
LRC workaround.

v2
- Fix commit description as lrc workaround instead of engine.(Lucas)

v3
- COMMON_SLICE_CHICKEN1 is a masked register, add XE_REG_OPTION_MASKED
flag. (Matt)

BSPEC: 55899

Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarHimal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240401163806.3821128-1-himal.prasad.ghimiray@intel.com
parent 62742d12

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+2 −1
Original line number Diff line number Diff line
@@ -97,7 +97,8 @@ 
#define CACHE_MODE_1				XE_REG(0x7004, XE_REG_OPTION_MASKED)

#define   MSAA_OPTIMIZATION_REDUC_DISABLE	REG_BIT(11)



#define COMMON_SLICE_CHICKEN1			XE_REG(0x7010)

#define COMMON_SLICE_CHICKEN1			XE_REG(0x7010, XE_REG_OPTION_MASKED)

#define   DISABLE_BOTTOM_CLIP_RECTANGLE_TEST	REG_BIT(14)



#define HIZ_CHICKEN					XE_REG(0x7018, XE_REG_OPTION_MASKED)

#define   DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE	REG_BIT(14)

drivers/gpu/drm/xe/xe_wa.c

+4 −0
Original line number Diff line number Diff line
@@ -579,6 +579,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = { 
		       ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT))

	},

	{ XE_RTP_NAME("18033852989"),

	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))

	},



	{}

};