Commit 9f1aa395 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/pwrctrl-tc9563' 

- Add a struct pci_ops.assert_perst() function pointer to assert/deassert
  PCIe PERST# and implement it for the qcom driver (Krishna Chaitanya
  Chundru)

- Add DT binding and pwrctrl driver for the Toshiba TC9563 PCIe switch,
  which must be held in reset after poweron so the pwrctrl driver can
  configure the switch via I2C before bringing up the links (Krishna
  Chaitanya Chundru)

* pci/pwrctrl-tc9563:
  PCI: pwrctrl: Add power control driver for TC9563
  PCI: qcom: Implement .assert_perst()
  PCI: dwc: Implement .assert_perst() for dwc glue drivers
  PCI: Add .assert_perst() to control PCIe PERST#
  dt-bindings: PCI: Add binding for Toshiba TC9563 PCIe switch
parents 7a13e837 4c9c7be4

Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/toshiba,tc9563.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Toshiba TC9563 PCIe switch



maintainers:

  - Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>



description: |

  Toshiba TC9563 PCIe switch has one upstream and three downstream ports.

  The 3rd downstream port has integrated endpoint device of Ethernet MAC.

  Other two downstream ports are supposed to connect to external device.



  The TC9563 PCIe switch can be configured through I2C interface before

  PCIe link is established to change FTS, ASPM related entry delays,

  tx amplitude etc for better power efficiency and functionality.



properties:

  compatible:

    enum:

      - pci1179,0623



  reg:

    maxItems: 1



  resx-gpios:

    maxItems: 1

    description:

      GPIO controlling the RESX# pin.



  vdd18-supply: true



  vdd09-supply: true



  vddc-supply: true



  vddio1-supply: true



  vddio2-supply: true



  vddio18-supply: true



  i2c-parent:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    description:

      A phandle to the parent I2C node and the slave address of the device

      used to configure tc9563 to change FTS, tx amplitude etc.

    items:

      - description: Phandle to the I2C controller node

      - description: I2C slave address



patternProperties:

  "^pcie@[1-3],0$":

    description:

      child nodes describing the internal downstream ports of

      the tc9563 switch.

    type: object

    allOf:

      - $ref: "#/$defs/tc9563-node"

      - $ref: /schemas/pci/pci-pci-bridge.yaml#

    unevaluatedProperties: false



$defs:

  tc9563-node:

    type: object



    properties:

      toshiba,tx-amplitude-microvolt:

        description:

          Change Tx Margin setting for low power consumption.



      toshiba,no-dfe-support:

        type: boolean

        description:

          Disable DFE (Decision Feedback Equalizer), which mitigates

          intersymbol interference and some reflections caused by

          impedance mismatches.



required:

  - resx-gpios

  - vdd18-supply

  - vdd09-supply

  - vddc-supply

  - vddio1-supply

  - vddio2-supply

  - vddio18-supply

  - i2c-parent



allOf:

  - $ref: "#/$defs/tc9563-node"

  - $ref: /schemas/pci/pci-bus-common.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/gpio/gpio.h>



    pcie {

        #address-cells = <3>;

        #size-cells = <2>;



        pcie@0 {

            device_type = "pci";

            reg = <0x0 0x0 0x0 0x0 0x0>;



            #address-cells = <3>;

            #size-cells = <2>;

            ranges;

            bus-range = <0x01 0xff>;



            pcie@0,0 {

                compatible = "pci1179,0623";



                reg = <0x10000 0x0 0x0 0x0 0x0>;

                device_type = "pci";

                #address-cells = <3>;

                #size-cells = <2>;

                ranges;

                bus-range = <0x02 0xff>;



                i2c-parent = <&qup_i2c 0x77>;



                vdd18-supply = <&vdd>;

                vdd09-supply = <&vdd>;

                vddc-supply = <&vdd>;

                vddio1-supply = <&vdd>;

                vddio2-supply = <&vdd>;

                vddio18-supply = <&vdd>;



                resx-gpios = <&gpio 1 GPIO_ACTIVE_LOW>;



                pcie@1,0 {

                    compatible = "pciclass,0604";

                    reg = <0x20800 0x0 0x0 0x0 0x0>;

                    #address-cells = <3>;

                    #size-cells = <2>;

                    device_type = "pci";

                    ranges;

                    bus-range = <0x03 0xff>;



                    toshiba,no-dfe-support;

                };



                pcie@2,0 {

                    compatible = "pciclass,0604";

                    reg = <0x21000 0x0 0x0 0x0 0x0>;

                    #address-cells = <3>;

                    #size-cells = <2>;

                    device_type = "pci";

                    ranges;

                    bus-range = <0x04 0xff>;

                };



                pcie@3,0 {

                    compatible = "pciclass,0604";

                    reg = <0x21800 0x0 0x0 0x0 0x0>;

                    #address-cells = <3>;

                    #size-cells = <2>;

                    device_type = "pci";

                    ranges;

                    bus-range = <0x05 0xff>;



                    toshiba,tx-amplitude-microvolt = <10>;



                    ethernet@0,0 {

                        reg = <0x50000 0x0 0x0 0x0 0x0>;

                    };



                    ethernet@0,1 {

                        reg = <0x50100 0x0 0x0 0x0 0x0>;

                    };

                };

            };

        };

    };

drivers/pci/controller/dwc/pcie-designware-host.c

+9 −0
Original line number Diff line number Diff line
@@ -843,10 +843,19 @@ void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, 
}

EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus);



static int dw_pcie_op_assert_perst(struct pci_bus *bus, bool assert)

{

	struct dw_pcie_rp *pp = bus->sysdata;

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);



	return dw_pcie_assert_perst(pci, assert);

}



static struct pci_ops dw_pcie_ops = {

	.map_bus = dw_pcie_own_conf_map_bus,

	.read = pci_generic_config_read,

	.write = pci_generic_config_write,

	.assert_perst = dw_pcie_op_assert_perst,

};



static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)

drivers/pci/controller/dwc/pcie-designware.h

+9 −0
Original line number Diff line number Diff line
@@ -493,6 +493,7 @@ struct dw_pcie_ops { 
	enum dw_pcie_ltssm (*get_ltssm)(struct dw_pcie *pcie);

	int	(*start_link)(struct dw_pcie *pcie);

	void	(*stop_link)(struct dw_pcie *pcie);

	int	(*assert_perst)(struct dw_pcie *pcie, bool assert);

};



struct debugfs_info {
@@ -797,6 +798,14 @@ static inline void dw_pcie_stop_link(struct dw_pcie *pci) 
		pci->ops->stop_link(pci);

}



static inline int dw_pcie_assert_perst(struct dw_pcie *pci, bool assert)

{

	if (pci->ops && pci->ops->assert_perst)

		return pci->ops->assert_perst(pci, assert);



	return 0;

}



static inline enum dw_pcie_ltssm dw_pcie_get_ltssm(struct dw_pcie *pci)

{

	u32 val;

drivers/pci/controller/dwc/pcie-qcom.c

+13 −0
Original line number Diff line number Diff line
@@ -696,6 +696,18 @@ static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie) 
	return 0;

}



static int qcom_pcie_assert_perst(struct dw_pcie *pci, bool assert)

{

	struct qcom_pcie *pcie = to_qcom_pcie(pci);



	if (assert)

		qcom_ep_reset_assert(pcie);

	else

		qcom_ep_reset_deassert(pcie);



	return 0;

}



static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)

{

	u32 val;
@@ -1518,6 +1530,7 @@ static const struct qcom_pcie_cfg cfg_fw_managed = { 
static const struct dw_pcie_ops dw_pcie_ops = {

	.link_up = qcom_pcie_link_up,

	.start_link = qcom_pcie_start_link,

	.assert_perst = qcom_pcie_assert_perst,

};



static int qcom_pcie_icc_init(struct qcom_pcie *pcie)

drivers/pci/pwrctrl/Kconfig

+15 −0
Original line number Diff line number Diff line
@@ -22,6 +22,21 @@ config PCI_PWRCTRL_SLOT 
	  PCI slots. The voltage regulators powering the rails of the PCI slots

	  are expected to be defined in the devicetree node of the PCI bridge.



config PCI_PWRCTRL_TC9563

	tristate "PCI Power Control driver for TC9563 PCIe switch"

	select PCI_PWRCTRL

	default m if ARCH_QCOM

	depends on I2C

	help

	  Say Y here to enable the PCI Power Control driver of TC9563 PCIe

	  switch.



	  This driver enables power and configures the TC9563 PCIe switch

	  through i2c. TC9563 is a PCIe switch which has one upstream and three

	  downstream ports. To one of the downstream ports integrated ethernet

	  MAC is connected as endpoint device. Other two downstream ports are

	  supposed to connect to external device.



# deprecated

config HAVE_PWRCTL

	bool