Commit 9f4bd5dd authored by James Courtier-Dutton's avatar James Courtier-Dutton Committed by Jaroslav Kysela
Browse files

[ALSA] snd-emu10k1: Added support for emu1010, including E-Mu 1212m and E-Mu 1820m 




Signed-off-by: default avatarJames Courtier-Dutton <James@superbug.co.uk>
Signed-off-by: default avatarJaroslav Kysela <perex@suse.cz>
parent 5986a2ec

include/sound/emu10k1.h

+313 −2
Original line number Diff line number Diff line
@@ -188,7 +188,35 @@ 
#define HCFG_LEGACYINT		0x00200000	/* 1 = legacy event captured. Write 1 to clear.	*/

						/* NOTE: The rest of the bits in this register	*/

						/* _are_ relevant under Linux.			*/

#define HCFG_CODECFORMAT_MASK	0x00070000	/* CODEC format					*/

#define HCFG_PUSH_BUTTON_ENABLE 0x00100000	/* Enables Volume Inc/Dec and Mute functions    */

#define HCFG_BAUD_RATE		0x00080000	/* 0 = 48kHz, 1 = 44.1kHz			*/

#define HCFG_EXPANDED_MEM	0x00040000	/* 1 = any 16M of 4G addr, 0 = 32M of 2G addr	*/

#define HCFG_CODECFORMAT_MASK	0x00030000	/* CODEC format					*/



/* Specific to Alice2, CA0102 */

#define HCFG_CODECFORMAT_AC97_1	0x00000000	/* AC97 CODEC format -- Ver 1.03		*/

#define HCFG_CODECFORMAT_AC97_2	0x00010000	/* AC97 CODEC format -- Ver 2.1			*/

#define HCFG_AUTOMUTE_ASYNC	0x00008000	/* When set, the async sample rate convertors	*/

						/* will automatically mute their output when	*/

						/* they are not rate-locked to the external	*/

						/* async audio source  				*/

#define HCFG_AUTOMUTE_SPDIF	0x00004000	/* When set, the async sample rate convertors	*/

						/* will automatically mute their output when	*/

						/* the SPDIF V-bit indicates invalid audio	*/

#define HCFG_EMU32_SLAVE	0x00002000	/* 0 = Master, 1 = Slave. Slave for EMU1010	*/

#define HCFG_SLOW_RAMP		0x00001000	/* Increases Send Smoothing time constant	*/

/* 0x00000800 not used on Alice2 */

#define HCFG_PHASE_TRACK_MASK	0x00000700	/* When set, forces corresponding input to	*/

						/* phase track the previous input.		*/

						/* I2S0 can phase track the last S/PDIF input	*/

#define HCFG_I2S_ASRC_ENABLE	0x00000070	/* When set, enables asynchronous sample rate   */

						/* conversion for the corresponding		*/

 						/* I2S format input				*/

/* Rest of HCFG 0x0000000f same as below. LOCKSOUNDCACHE etc.  */







/* Older chips */

#define HCFG_CODECFORMAT_AC97	0x00000000	/* AC97 CODEC format -- Primary Output		*/

#define HCFG_CODECFORMAT_I2S	0x00010000	/* I2S CODEC format -- Secondary (Rear) Output	*/

#define HCFG_GPINPUT0		0x00004000	/* External pin112				*/
@@ -886,6 +914,280 @@ 
#define A_HIWORD_RESULT_MASK	0x007ff000

#define A_HIWORD_OPA_MASK	0x000007ff



/************************************************************************************************/

/* EMU1010m HANA FPGA registers									*/

/************************************************************************************************/

#define EMU_HANA_DESTHI		0x00	/* 0000xxx  3 bits Link Destination */

#define EMU_HANA_DESTLO		0x01	/* 00xxxxx  5 bits */

#define EMU_HANA_SRCHI		0x02	/* 0000xxx  3 bits Link Source */

#define EMU_HANA_SRCLO		0x03	/* 00xxxxx  5 bits */

#define EMU_HANA_DOCK_PWR	0x04	/* 000000x  1 bits Audio Dock power */

#define EMU_HANA_DOCK_PWR_ON		0x01 /* Audio Dock power on */

#define EMU_HANA_WCLOCK		0x05	/* 0000xxx  3 bits Word Clock source select  */

					/* Must be written after power on to reset DLL */

					/* One is unable to detect the Audio dock without this */

#define EMU_HANA_WCLOCK_SRC_MASK	0x07

#define EMU_HANA_WCLOCK_INT_48K		0x00

#define EMU_HANA_WCLOCK_INT_44_1K	0x01

#define EMU_HANA_WCLOCK_HANA_SPDIF_IN	0x02

#define EMU_HANA_WCLOCK_HANA_ADAT_IN	0x03

#define EMU_HANA_WCLOCK_SYNC_BNCN	0x04

#define EMU_HANA_WCLOCK_2ND_HANA	0x05

#define EMU_HANA_WCLOCK_SRC_RESERVED	0x06

#define EMU_HANA_WCLOCK_OFF		0x07 /* For testing, forces fallback to DEFCLOCK */

#define EMU_HANA_WCLOCK_MULT_MASK	0x18

#define EMU_HANA_WCLOCK_1X		0x00

#define EMU_HANA_WCLOCK_2X		0x08

#define EMU_HANA_WCLOCK_4X		0x10

#define EMU_HANA_WCLOCK_MULT_RESERVED	0x18



#define EMU_HANA_DEFCLOCK	0x06	/* 000000x  1 bits Default Word Clock  */

#define EMU_HANA_DEFCLOCK_48K		0x00

#define EMU_HANA_DEFCLOCK_44_1K		0x01



#define EMU_HANA_UNMUTE		0x07	/* 000000x  1 bits Mute all audio outputs  */

#define EMU_MUTE			0x00

#define EMU_UNMUTE			0x01



#define EMU_HANA_FPGA_CONFIG	0x08	/* 00000xx  2 bits Config control of FPGAs  */

#define EMU_HANA_FPGA_CONFIG_AUDIODOCK	0x01 /* Set in order to program FPGA on Audio Dock */

#define EMU_HANA_FPGA_CONFIG_HANA	0x02 /* Set in order to program FPGA on Hana */



#define EMU_HANA_IRQ_ENABLE	0x09	/* 000xxxx  4 bits IRQ Enable  */

#define EMU_HANA_IRQ_WCLK_CHANGED	0x01

#define EMU_HANA_IRQ_ADAT		0x02

#define EMU_HANA_IRQ_DOCK		0x04

#define EMU_HANA_IRQ_DOCK_LOST		0x08



#define EMU_HANA_SPDIF_MODE	0x0a	/* 00xxxxx  5 bits SPDIF MODE  */

#define EMU_HANA_SPDIF_MODE_TX_COMSUMER	0x00

#define EMU_HANA_SPDIF_MODE_TX_PRO	0x01

#define EMU_HANA_SPDIF_MODE_TX_NOCOPY	0x02

#define EMU_HANA_SPDIF_MODE_RX_COMSUMER	0x00

#define EMU_HANA_SPDIF_MODE_RX_PRO	0x04

#define EMU_HANA_SPDIF_MODE_RX_NOCOPY	0x08

#define EMU_HANA_SPDIF_MODE_RX_INVALID	0x10



#define EMU_HANA_OPTICAL_TYPE	0x0b	/* 00000xx  2 bits ADAT or SPDIF in/out  */

#define EMU_HANA_OPTICAL_IN_SPDIF	0x00

#define EMU_HANA_OPTICAL_IN_ADAT	0x01

#define EMU_HANA_OPTICAL_OUT_SPDIF	0x00

#define EMU_HANA_OPTICAL_OUT_ADAT	0x02



#define EMU_HANA_MIDI		0x0c	/* 000000x  1 bit  Control MIDI  */

#define EMU_HANA_MIDI_IN_FROM_HAMOA	0x00 /* HAMOA MIDI in to Alice 2 MIDI B */

#define EMU_HANA_MIDI_IN_FROM_DOCK	0x01 /* Audio Dock MIDI in to Alice 2 MIDI B */



#define EMU_HANA_DOCK_LEDS_1	0x0d	/* 000xxxx  4 bit  Audio Dock LEDs  */

#define EMU_HANA_DOCK_LEDS_1_MIDI1	0x01	/* MIDI 1 LED on */

#define EMU_HANA_DOCK_LEDS_1_MIDI2	0x02	/* MIDI 2 LED on */

#define EMU_HANA_DOCK_LEDS_1_SMPTE_IN	0x04	/* SMPTE IN LED on */

#define EMU_HANA_DOCK_LEDS_1_SMPTE_OUT	0x08	/* SMPTE OUT LED on */



#define EMU_HANA_DOCK_LEDS_2	0x0e	/* 0xxxxxx  6 bit  Audio Dock LEDs  */

#define EMU_HANA_DOCK_LEDS_2_44K	0x01	/* 44.1 kHz LED on */

#define EMU_HANA_DOCK_LEDS_2_48K	0x02	/* 48 kHz LED on */

#define EMU_HANA_DOCK_LEDS_2_96K	0x04	/* 96 kHz LED on */

#define EMU_HANA_DOCK_LEDS_2_192K	0x08	/* 192 kHz LED on */

#define EMU_HANA_DOCK_LEDS_2_LOCK	0x10	/* LOCK LED on */

#define EMU_HANA_DOCK_LEDS_2_EXT	0x20	/* EXT LED on */



#define EMU_HANA_DOCK_LEDS_3	0x0f	/* 0xxxxxx  6 bit  Audio Dock LEDs  */

#define EMU_HANA_DOCK_LEDS_3_CLIP_A	0x01	/* Mic A Clip LED on */

#define EMU_HANA_DOCK_LEDS_3_CLIP_B	0x02	/* Mic B Clip LED on */

#define EMU_HANA_DOCK_LEDS_3_SIGNAL_A	0x04	/* Signal A Clip LED on */

#define EMU_HANA_DOCK_LEDS_3_SIGNAL_B	0x08	/* Signal B Clip LED on */

#define EMU_HANA_DOCK_LEDS_3_MANUAL_CLIP	0x10	/* Manual Clip detection */

#define EMU_HANA_DOCK_LEDS_3_MANUAL_SIGNAL	0x20	/* Manual Signal detection */



#define EMU_HANA_DOCK_PADS	0x10	/* 0000xxx  3 bit  Audio Dock ADC 14dB pads */

#define EMU_HANA_DOCK_PAD1	0x01	/* 14dB Attenuation on ADC 1 */

#define EMU_HANA_DOCK_PAD2	0x02	/* 14dB Attenuation on ADC 2 */

#define EMU_HANA_DOCK_PAD3	0x04	/* 14dB Attenuation on ADC 3 */



#define EMU_HANA_DOCK_MISC	0x11	/* 0xxxxxx  6 bit  Audio Dock misc bits */

#define EMU_HANA_DOCK_DAC1_MUTE	0x01	/* DAC 1 Mute */

#define EMU_HANA_DOCK_DAC2_MUTE	0x02	/* DAC 2 Mute */

#define EMU_HANA_DOCK_DAC3_MUTE	0x04	/* DAC 3 Mute */

#define EMU_HANA_DOCK_DAC4_MUTE	0x08	/* DAC 4 Mute */

#define EMU_HANA_DOCK_PHONES_192_DAC1	0x00	/* DAC 1 Headphones source at 192kHz */

#define EMU_HANA_DOCK_PHONES_192_DAC2	0x10	/* DAC 2 Headphones source at 192kHz */

#define EMU_HANA_DOCK_PHONES_192_DAC3	0x20	/* DAC 3 Headphones source at 192kHz */

#define EMU_HANA_DOCK_PHONES_192_DAC4	0x30	/* DAC 4 Headphones source at 192kHz */



#define EMU_HANA_UNKNOWN12	0x12	/* 0xxxxxx  6 bit  Unknown12 */

#define EMU_HANA_UNKNOWN13	0x13	/* 0xxxxxx  6 bit  Unknown13 */

/* 0x14 - 0x1f Unused R/W registers */

#define EMU_HANA_IRQ_STATUS	0x20	/* 000xxxx  4 bits IRQ Status  */

#if 0  /* Already defined for reg 0x09 IRQ_ENABLE */

#define EMU_HANA_IRQ_WCLK_CHANGED	0x01

#define EMU_HANA_IRQ_ADAT		0x02

#define EMU_HANA_IRQ_DOCK		0x04

#define EMU_HANA_IRQ_DOCK_LOST		0x08

#endif



#define EMU_HANA_OPTION_CARDS	0x21	/* 000xxxx  4 bits Presence of option cards */

#define EMU_HANA_OPTION_HAMOA	0x01	/* HAMOA card present */

#define EMU_HANA_OPTION_SYNC	0x02	/* Sync card present */

#define EMU_HANA_OPTION_DOCK_ONLINE	0x04	/* Audio Dock online and FPGA configured */

#define EMU_HANA_OPTION_DOCK_OFFLINE	0x08	/* Audio Dock online and FPGA not configured */



#define EMU_HANA_ID		0x22	/* 1010101  7 bits ID byte & 0x7f = 0x55 */



#define EMU_HANA_MAJOR_REV	0x23	/* 0000xxx  3 bit  Hana FPGA Major rev */

#define EMU_HANA_MINOR_REV	0x24	/* 0000xxx  3 bit  Hana FPGA Minor rev */



#define EMU_DOCK_MAJOR_REV	0x25	/* 0000xxx  3 bit  Audio Dock FPGA Major rev */

#define EMU_DOCK_MINOR_REV	0x26	/* 0000xxx  3 bit  Audio Dock FPGA Minor rev */



#define EMU_DOCK_BOARD_ID	0x27	/* 00000xx  2 bits Audio Dock ID pins */

#define EMU_DOCK_BOARD_ID0	0x00	/* ID bit 0 */

#define EMU_DOCK_BOARD_ID1	0x03	/* ID bit 1 */



#define EMU_HANA_WC_SPDIF_HI	0x28	/* 0xxxxxx  6 bit  SPDIF IN Word clock, upper 6 bits */

#define EMU_HANA_WC_SPDIF_LO	0x29	/* 0xxxxxx  6 bit  SPDIF IN Word clock, lower 6 bits */



#define EMU_HANA_WC_ADAT_HI	0x2a	/* 0xxxxxx  6 bit  ADAT IN Word clock, upper 6 bits */

#define EMU_HANA_WC_ADAT_LO	0x2b	/* 0xxxxxx  6 bit  ADAT IN Word clock, lower 6 bits */



#define EMU_HANA_WC_BNC_LO	0x2c	/* 0xxxxxx  6 bit  BNC IN Word clock, lower 6 bits */

#define EMU_HANA_WC_BNC_HI	0x2d	/* 0xxxxxx  6 bit  BNC IN Word clock, upper 6 bits */



#define EMU_HANA2_WC_SPDIF_HI	0x2e	/* 0xxxxxx  6 bit  HANA2 SPDIF IN Word clock, upper 6 bits */

#define EMU_HANA2_WC_SPDIF_LO	0x2f	/* 0xxxxxx  6 bit  HANA2 SPDIF IN Word clock, lower 6 bits */

/* 0x30 - 0x3f Unused Read only registers */



/************************************************************************************************/

/* EMU1010m HANA Destinations									*/

/************************************************************************************************/

#define EMU_DST_ALICE2_EMU32_0	0x000f	/* 16 EMU32 channels to Alice2 +0 to +0xf */

#define EMU_DST_ALICE2_EMU32_1	0x0000	/* 16 EMU32 channels to Alice2 +0 to +0xf */

#define EMU_DST_ALICE2_EMU32_2	0x0001	/* 16 EMU32 channels to Alice2 +0 to +0xf */

#define EMU_DST_ALICE2_EMU32_3	0x0002	/* 16 EMU32 channels to Alice2 +0 to +0xf */

#define EMU_DST_ALICE2_EMU32_4	0x0003	/* 16 EMU32 channels to Alice2 +0 to +0xf */

#define EMU_DST_ALICE2_EMU32_5	0x0004	/* 16 EMU32 channels to Alice2 +0 to +0xf */

#define EMU_DST_ALICE2_EMU32_6	0x0005	/* 16 EMU32 channels to Alice2 +0 to +0xf */

#define EMU_DST_ALICE2_EMU32_7	0x0006	/* 16 EMU32 channels to Alice2 +0 to +0xf */

#define EMU_DST_ALICE2_EMU32_8	0x0007	/* 16 EMU32 channels to Alice2 +0 to +0xf */

#define EMU_DST_ALICE2_EMU32_9	0x0008	/* 16 EMU32 channels to Alice2 +0 to +0xf */

#define EMU_DST_ALICE2_EMU32_A	0x0009	/* 16 EMU32 channels to Alice2 +0 to +0xf */

#define EMU_DST_ALICE2_EMU32_B	0x000a	/* 16 EMU32 channels to Alice2 +0 to +0xf */

#define EMU_DST_ALICE2_EMU32_C	0x000b	/* 16 EMU32 channels to Alice2 +0 to +0xf */

#define EMU_DST_ALICE2_EMU32_D	0x000c	/* 16 EMU32 channels to Alice2 +0 to +0xf */

#define EMU_DST_ALICE2_EMU32_E	0x000d	/* 16 EMU32 channels to Alice2 +0 to +0xf */

#define EMU_DST_ALICE2_EMU32_F	0x000e	/* 16 EMU32 channels to Alice2 +0 to +0xf */

#define EMU_DST_DOCK_DAC1_LEFT1	0x0100	/* Audio Dock DAC1 Left, 1st or 48kHz only */

#define EMU_DST_DOCK_DAC1_LEFT2	0x0101	/* Audio Dock DAC1 Left, 2nd or 96kHz */

#define EMU_DST_DOCK_DAC1_LEFT3	0x0102	/* Audio Dock DAC1 Left, 3rd or 192kHz */

#define EMU_DST_DOCK_DAC1_LEFT4	0x0103	/* Audio Dock DAC1 Left, 4th or 192kHz */

#define EMU_DST_DOCK_DAC1_RIGHT1	0x0104	/* Audio Dock DAC1 Right, 1st or 48kHz only */

#define EMU_DST_DOCK_DAC1_RIGHT2	0x0105	/* Audio Dock DAC1 Right, 2nd or 96kHz */

#define EMU_DST_DOCK_DAC1_RIGHT3	0x0106	/* Audio Dock DAC1 Right, 3rd or 192kHz */

#define EMU_DST_DOCK_DAC1_RIGHT4	0x0107	/* Audio Dock DAC1 Right, 4th or 192kHz */

#define EMU_DST_DOCK_DAC2_LEFT1	0x0108	/* Audio Dock DAC2 Left, 1st or 48kHz only */

#define EMU_DST_DOCK_DAC2_LEFT2	0x0109	/* Audio Dock DAC2 Left, 2nd or 96kHz */

#define EMU_DST_DOCK_DAC2_LEFT3	0x010a	/* Audio Dock DAC2 Left, 3rd or 192kHz */

#define EMU_DST_DOCK_DAC2_LEFT4	0x010b	/* Audio Dock DAC2 Left, 4th or 192kHz */

#define EMU_DST_DOCK_DAC2_RIGHT1	0x010c	/* Audio Dock DAC2 Right, 1st or 48kHz only */

#define EMU_DST_DOCK_DAC2_RIGHT2	0x010d	/* Audio Dock DAC2 Right, 2nd or 96kHz */

#define EMU_DST_DOCK_DAC2_RIGHT3	0x010e	/* Audio Dock DAC2 Right, 3rd or 192kHz */

#define EMU_DST_DOCK_DAC2_RIGHT4	0x010f	/* Audio Dock DAC2 Right, 4th or 192kHz */

#define EMU_DST_DOCK_DAC3_LEFT1	0x0110	/* Audio Dock DAC1 Left, 1st or 48kHz only */

#define EMU_DST_DOCK_DAC3_LEFT2	0x0111	/* Audio Dock DAC1 Left, 2nd or 96kHz */

#define EMU_DST_DOCK_DAC3_LEFT3	0x0112	/* Audio Dock DAC1 Left, 3rd or 192kHz */

#define EMU_DST_DOCK_DAC3_LEFT4	0x0113	/* Audio Dock DAC1 Left, 4th or 192kHz */

#define EMU_DST_DOCK_PHONES_LEFT1	0x0112	/* Audio Dock PHONES Left, 1st or 48kHz only */

#define EMU_DST_DOCK_PHONES_LEFT2	0x0113	/* Audio Dock PHONES Left, 2nd or 96kHz */

#define EMU_DST_DOCK_DAC3_RIGHT1	0x0114	/* Audio Dock DAC1 Right, 1st or 48kHz only */

#define EMU_DST_DOCK_DAC3_RIGHT2	0x0115	/* Audio Dock DAC1 Right, 2nd or 96kHz */

#define EMU_DST_DOCK_DAC3_RIGHT3	0x0116	/* Audio Dock DAC1 Right, 3rd or 192kHz */

#define EMU_DST_DOCK_DAC3_RIGHT4	0x0117	/* Audio Dock DAC1 Right, 4th or 192kHz */

#define EMU_DST_DOCK_PHONES_RIGHT1	0x0116	/* Audio Dock PHONES Right, 1st or 48kHz only */

#define EMU_DST_DOCK_PHONES_RIGHT2	0x0117	/* Audio Dock PHONES Right, 2nd or 96kHz */

#define EMU_DST_DOCK_DAC4_LEFT1	0x0118	/* Audio Dock DAC2 Left, 1st or 48kHz only */

#define EMU_DST_DOCK_DAC4_LEFT2	0x0119	/* Audio Dock DAC2 Left, 2nd or 96kHz */

#define EMU_DST_DOCK_DAC4_LEFT3	0x011a	/* Audio Dock DAC2 Left, 3rd or 192kHz */

#define EMU_DST_DOCK_DAC4_LEFT4	0x011b	/* Audio Dock DAC2 Left, 4th or 192kHz */

#define EMU_DST_DOCK_SPDIF_LEFT1	0x011a	/* Audio Dock SPDIF Left, 1st or 48kHz only */

#define EMU_DST_DOCK_SPDIF_LEFT2	0x011b	/* Audio Dock SPDIF Left, 2nd or 96kHz */

#define EMU_DST_DOCK_DAC4_RIGHT1	0x011c	/* Audio Dock DAC2 Right, 1st or 48kHz only */

#define EMU_DST_DOCK_DAC4_RIGHT2	0x011d	/* Audio Dock DAC2 Right, 2nd or 96kHz */

#define EMU_DST_DOCK_DAC4_RIGHT3	0x011e	/* Audio Dock DAC2 Right, 3rd or 192kHz */

#define EMU_DST_DOCK_DAC4_RIGHT4	0x011f	/* Audio Dock DAC2 Right, 4th or 192kHz */

#define EMU_DST_DOCK_SPDIF_RIGHT1	0x011e	/* Audio Dock SPDIF Right, 1st or 48kHz only */

#define EMU_DST_DOCK_SPDIF_RIGHT2	0x011f	/* Audio Dock SPDIF Right, 2nd or 96kHz */

#define EMU_DST_HANA_SPDIF_LEFT1	0x0200	/* Hana SPDIF Left, 1st or 48kHz only */

#define EMU_DST_HANA_SPDIF_LEFT2	0x0202	/* Hana SPDIF Left, 2nd or 96kHz */

#define EMU_DST_HANA_SPDIF_RIGHT1	0x0201	/* Hana SPDIF Right, 1st or 48kHz only */

#define EMU_DST_HANA_SPDIF_RIGHT2	0x0203	/* Hana SPDIF Right, 2nd or 96kHz */

#define EMU_DST_HAMOA_DAC_LEFT1	0x0300	/* Hamoa DAC Left, 1st or 48kHz only */

#define EMU_DST_HAMOA_DAC_LEFT2	0x0302	/* Hamoa DAC Left, 2nd or 96kHz */

#define EMU_DST_HAMOA_DAC_LEFT3	0x0304	/* Hamoa DAC Left, 3rd or 192kHz */

#define EMU_DST_HAMOA_DAC_LEFT4	0x0306	/* Hamoa DAC Left, 4th or 192kHz */

#define EMU_DST_HAMOA_DAC_RIGHT1	0x0301	/* Hamoa DAC Right, 1st or 48kHz only */

#define EMU_DST_HAMOA_DAC_RIGHT2	0x0303	/* Hamoa DAC Right, 2nd or 96kHz */

#define EMU_DST_HAMOA_DAC_RIGHT3	0x0305	/* Hamoa DAC Right, 3rd or 192kHz */

#define EMU_DST_HAMOA_DAC_RIGHT4	0x0307	/* Hamoa DAC Right, 4th or 192kHz */

#define EMU_DST_HANA_ADAT	0x0400	/* Hana ADAT 8 channel out +0 to +7 */

#define EMU_DST_ALICE_I2S0_LEFT		0x0500	/* Alice2 I2S0 Left */

#define EMU_DST_ALICE_I2S0_RIGHT	0x0501	/* Alice2 I2S0 Right */

#define EMU_DST_ALICE_I2S1_LEFT		0x0600	/* Alice2 I2S1 Left */

#define EMU_DST_ALICE_I2S1_RIGHT	0x0601	/* Alice2 I2S1 Right */

#define EMU_DST_ALICE_I2S2_LEFT		0x0700	/* Alice2 I2S2 Left */

#define EMU_DST_ALICE_I2S2_RIGHT	0x0701	/* Alice2 I2S2 Right */



/************************************************************************************************/

/* EMU1010m HANA Sources									*/

/************************************************************************************************/

#define EMU_SRC_SILENCE		0x0000	/* Silence */

#define EMU_SRC_DOCK_MIC_A1	0x0100	/* Audio Dock Mic A, 1st or 48kHz only */

#define EMU_SRC_DOCK_MIC_A2	0x0101	/* Audio Dock Mic A, 2nd or 96kHz */

#define EMU_SRC_DOCK_MIC_A3	0x0102	/* Audio Dock Mic A, 3rd or 192kHz */

#define EMU_SRC_DOCK_MIC_A4	0x0103	/* Audio Dock Mic A, 4th or 192kHz */

#define EMU_SRC_DOCK_MIC_B1	0x0104	/* Audio Dock Mic B, 1st or 48kHz only */

#define EMU_SRC_DOCK_MIC_B2	0x0105	/* Audio Dock Mic B, 2nd or 96kHz */

#define EMU_SRC_DOCK_MIC_B3	0x0106	/* Audio Dock Mic B, 3rd or 192kHz */

#define EMU_SRC_DOCK_MIC_B4	0x0107	/* Audio Dock Mic B, 4th or 192kHz */

#define EMU_SRC_DOCK_ADC1_LEFT1	0x0108	/* Audio Dock ADC1 Left, 1st or 48kHz only */

#define EMU_SRC_DOCK_ADC1_LEFT2	0x0109	/* Audio Dock ADC1 Left, 2nd or 96kHz */

#define EMU_SRC_DOCK_ADC1_LEFT3	0x010a	/* Audio Dock ADC1 Left, 3rd or 192kHz */

#define EMU_SRC_DOCK_ADC1_LEFT4	0x010b	/* Audio Dock ADC1 Left, 4th or 192kHz */

#define EMU_SRC_DOCK_ADC1_RIGHT1	0x010c	/* Audio Dock ADC1 Right, 1st or 48kHz only */

#define EMU_SRC_DOCK_ADC1_RIGHT2	0x010d	/* Audio Dock ADC1 Right, 2nd or 96kHz */

#define EMU_SRC_DOCK_ADC1_RIGHT3	0x010e	/* Audio Dock ADC1 Right, 3rd or 192kHz */

#define EMU_SRC_DOCK_ADC1_RIGHT4	0x010f	/* Audio Dock ADC1 Right, 4th or 192kHz */

#define EMU_SRC_DOCK_ADC2_LEFT1	0x0110	/* Audio Dock ADC2 Left, 1st or 48kHz only */

#define EMU_SRC_DOCK_ADC2_LEFT2	0x0111	/* Audio Dock ADC2 Left, 2nd or 96kHz */

#define EMU_SRC_DOCK_ADC2_LEFT3	0x0112	/* Audio Dock ADC2 Left, 3rd or 192kHz */

#define EMU_SRC_DOCK_ADC2_LEFT4	0x0113	/* Audio Dock ADC2 Left, 4th or 192kHz */

#define EMU_SRC_DOCK_ADC2_RIGHT1	0x0114	/* Audio Dock ADC2 Right, 1st or 48kHz only */

#define EMU_SRC_DOCK_ADC2_RIGHT2	0x0115	/* Audio Dock ADC2 Right, 2nd or 96kHz */

#define EMU_SRC_DOCK_ADC2_RIGHT3	0x0116	/* Audio Dock ADC2 Right, 3rd or 192kHz */

#define EMU_SRC_DOCK_ADC2_RIGHT4	0x0117	/* Audio Dock ADC2 Right, 4th or 192kHz */

#define EMU_SRC_DOCK_ADC3_LEFT1	0x0118	/* Audio Dock ADC3 Left, 1st or 48kHz only */

#define EMU_SRC_DOCK_ADC3_LEFT2	0x0119	/* Audio Dock ADC3 Left, 2nd or 96kHz */

#define EMU_SRC_DOCK_ADC3_LEFT3	0x011a	/* Audio Dock ADC3 Left, 3rd or 192kHz */

#define EMU_SRC_DOCK_ADC3_LEFT4	0x011b	/* Audio Dock ADC3 Left, 4th or 192kHz */

#define EMU_SRC_DOCK_ADC3_RIGHT1	0x011c	/* Audio Dock ADC3 Right, 1st or 48kHz only */

#define EMU_SRC_DOCK_ADC3_RIGHT2	0x011d	/* Audio Dock ADC3 Right, 2nd or 96kHz */

#define EMU_SRC_DOCK_ADC3_RIGHT3	0x011e	/* Audio Dock ADC3 Right, 3rd or 192kHz */

#define EMU_SRC_DOCK_ADC3_RIGHT4	0x011f	/* Audio Dock ADC3 Right, 4th or 192kHz */

#define EMU_SRC_HAMOA_ADC_LEFT1	0x0200	/* Hamoa ADC Left, 1st or 48kHz only */

#define EMU_SRC_HAMOA_ADC_LEFT2	0x0202	/* Hamoa ADC Left, 2nd or 96kHz */

#define EMU_SRC_HAMOA_ADC_LEFT3	0x0204	/* Hamoa ADC Left, 3rd or 192kHz */

#define EMU_SRC_HAMOA_ADC_LEFT4	0x0206	/* Hamoa ADC Left, 4th or 192kHz */

#define EMU_SRC_HAMOA_ADC_RIGHT1	0x0201	/* Hamoa ADC Right, 1st or 48kHz only */

#define EMU_SRC_HAMOA_ADC_RIGHT2	0x0203	/* Hamoa ADC Right, 2nd or 96kHz */

#define EMU_SRC_HAMOA_ADC_RIGHT3	0x0205	/* Hamoa ADC Right, 3rd or 192kHz */

#define EMU_SRC_HAMOA_ADC_RIGHT4	0x0207	/* Hamoa ADC Right, 4th or 192kHz */

#define EMU_SRC_ALICE_EMU32A		0x0300	/* Alice2 EMU32a 16 outputs. +0 to +0xf */

#define EMU_SRC_ALICE_EMU32B		0x0310	/* Alice2 EMU32b 16 outputs. +0 to +0xf */

#define EMU_SRC_HANA_ADAT	0x0400	/* Hana ADAT 8 channel in +0 to +7 */

#define EMU_SRC_HANA_SPDIF_LEFT1	0x0500	/* Hana SPDIF Left, 1st or 48kHz only */

#define EMU_SRC_HANA_SPDIF_LEFT2	0x0502	/* Hana SPDIF Left, 2nd or 96kHz */

#define EMU_SRC_HANA_SPDIF_RIGHT1	0x0501	/* Hana SPDIF Right, 1st or 48kHz only */

#define EMU_SRC_HANA_SPDIF_RIGHT2	0x0503	/* Hana SPDIF Right, 2nd or 96kHz */

/* 0x600 and 0x700 no used */



/* ------------------- STRUCTURES -------------------- */
@@ -1063,7 +1365,7 @@ struct snd_emu_chip_details { 
	unsigned char spdif_bug;    /* Has Spdif phasing bug */

	unsigned char ac97_chip;    /* Has an AC97 chip: 1 = mandatory, 2 = optional */

	unsigned char ecard;        /* APS EEPROM */

	unsigned char emu1212m;     /* EMU 1212m card */

	unsigned char emu1010;     /* EMU 1010m card */

	unsigned char spi_dac;      /* SPI interface for DAC */

	unsigned char i2c_adc;      /* I2C interface for ADC */

	unsigned char adc_1361t;    /* Use Philips 1361T ADC */
@@ -1072,6 +1374,11 @@ struct snd_emu_chip_details { 
	const char *id;		/* for backward compatibility - can be NULL if not needed */

};



struct snd_emu1010 {

	unsigned int output_source[64];

	unsigned int input_source[64];

};



struct snd_emu10k1 {

	int irq;
@@ -1132,6 +1439,7 @@ struct snd_emu10k1 { 
	int p16v_device_offset;

	u32 p16v_capture_source;

	u32 p16v_capture_channel;

        struct snd_emu1010 emu1010;

	struct snd_emu10k1_pcm_mixer pcm_mixer[32];

	struct snd_emu10k1_pcm_mixer efx_pcm_mixer[NUM_EFX_PLAYBACK];

	struct snd_kcontrol *ctl_send_routing;
@@ -1208,6 +1516,9 @@ void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned i 
unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn);

void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data);

int snd_emu10k1_spi_write(struct snd_emu10k1 * emu, unsigned int data);

int snd_emu1010_fpga_write(struct snd_emu10k1 * emu, int reg, int value);

int snd_emu1010_fpga_read(struct snd_emu10k1 * emu, int reg, int *value);

int snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 * emu, int dst, int src);

unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc);

void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb);

void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb);

sound/pci/emu10k1/emu10k1_main.c

+418 −122

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sound/pci/emu10k1/emufx.c

+90 −12

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sound/pci/emu10k1/emumixer.c

+324 −1

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sound/pci/emu10k1/emupcm.c

+97 −30

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