Commit 9f7e8fbb authored Apr 09, 2024 by Michael Liang Committed by Jakub Kicinski Apr 10, 2024

net/mlx5: offset comp irq index in name by one



The mlx5 comp irq name scheme is changed a little bit between
commit 3663ad34 ("net/mlx5: Shift control IRQ to the last index")
and commit 3354822c ("net/mlx5: Use dynamic msix vectors allocation").
The index in the comp irq name used to start from 0 but now it starts
from 1. There is nothing critical here, but it's harmless to change
back to the old behavior, a.k.a starting from 0.

Fixes: 3354822c ("net/mlx5: Use dynamic msix vectors allocation")
Reviewed-by: Mohamed Khalfella <mkhalfella@purestorage.com>
Reviewed-by: Yuanyuan Zhong <yzhong@purestorage.com>
Signed-off-by: Michael Liang <mliang@purestorage.com>
Reviewed-by: Shay Drory <shayd@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://lore.kernel.org/r/20240409190820.227554-4-tariqt@nvidia.com


Signed-off-by: Jakub Kicinski <kuba@kernel.org>

parent c6e77aa9

drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c

+3 −1

Original line number	Diff line number	Diff line
		@@ -19,6 +19,7 @@
		#define MLX5_IRQ_CTRL_SF_MAX 8
		/* min num of vectors for SFs to be enabled */
		#define MLX5_IRQ_VEC_COMP_BASE_SF 2
		#define MLX5_IRQ_VEC_COMP_BASE 1

		#define MLX5_EQ_SHARE_IRQ_MAX_COMP (8)
		#define MLX5_EQ_SHARE_IRQ_MAX_CTRL (UINT_MAX)
		@@ -246,6 +247,7 @@ static void irq_set_name(struct mlx5_irq_pool pool, char name, int vecidx)
		return;
		}

		vecidx -= MLX5_IRQ_VEC_COMP_BASE;
		snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", vecidx);
		}

		@@ -585,7 +587,7 @@ struct mlx5_irq mlx5_irq_request_vector(struct mlx5_core_dev dev, u16 cpu,
		struct mlx5_irq_table *table = mlx5_irq_table_get(dev);
		struct mlx5_irq_pool *pool = table->pcif_pool;
		struct irq_affinity_desc af_desc;
		int offset = 1;
		int offset = MLX5_IRQ_VEC_COMP_BASE;

		if (!pool->xa_num_irqs.max)
		offset = 0;