Commit 9f9039c6 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2024-04-30' of... 

Merge tag 'drm-intel-next-2024-04-30' of https://anongit.freedesktop.org/git/drm/drm-intel

 into drm-next

Core DRM:
- Export drm_client_dev_unregister (Thomas Zimmermann)

Display i915:
- More initial work to make display code more independent from i915 (Jani)
- Convert i915/xe fbdev to DRM client (Thomas Zimmermann)
- VLV/CHV DPIO register cleanup (Ville)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZjFPcSCTd_5c0XU_@intel.com
parents 4a56c0ed 6f1923f5

drivers/gpu/drm/drm_client.c

+13 −0
Original line number Diff line number Diff line
@@ -172,6 +172,18 @@ void drm_client_release(struct drm_client_dev *client) 
}

EXPORT_SYMBOL(drm_client_release);



/**

 * drm_client_dev_unregister - Unregister clients

 * @dev: DRM device

 *

 * This function releases all clients by calling each client's

 * &drm_client_funcs.unregister callback. The callback function

 * is responsibe for releaseing all resources including the client

 * itself.

 *

 * The helper drm_dev_unregister() calls this function. Drivers

 * that use it don't need to call this function themselves.

 */

void drm_client_dev_unregister(struct drm_device *dev)

{

	struct drm_client_dev *client, *tmp;
@@ -191,6 +203,7 @@ void drm_client_dev_unregister(struct drm_device *dev) 
	}

	mutex_unlock(&dev->clientlist_mutex);

}

EXPORT_SYMBOL(drm_client_dev_unregister);



/**

 * drm_client_dev_hotplug - Send hotplug event to clients

drivers/gpu/drm/i915/display/intel_audio_regs.h

+16 −0
Original line number Diff line number Diff line
@@ -148,4 +148,20 @@ 
#define HBLANK_START_COUNT_96	4

#define HBLANK_START_COUNT_128	5



/* LPE Audio */

#define I915_HDMI_LPE_AUDIO_BASE	(VLV_DISPLAY_BASE + 0x65000)

#define I915_HDMI_LPE_AUDIO_SIZE	0x1000



#define VLV_AUD_CHICKEN_BIT_REG		_MMIO(VLV_DISPLAY_BASE + 0x62F38)

#define VLV_CHICKEN_BIT_DBG_ENABLE	(1 << 0)



#define _VLV_AUD_PORT_EN_B_DBG		0x62F20

#define _VLV_AUD_PORT_EN_C_DBG		0x62F30

#define _VLV_AUD_PORT_EN_D_DBG		0x62F34

#define VLV_AUD_PORT_EN_DBG(port)	_MMIO_BASE_PORT3(VLV_DISPLAY_BASE, (port) - PORT_B, \

							 _VLV_AUD_PORT_EN_B_DBG, \

							 _VLV_AUD_PORT_EN_C_DBG, \

							 _VLV_AUD_PORT_EN_D_DBG)

#define VLV_AMP_MUTE		        (1 << 1)



#endif /* __INTEL_AUDIO_REGS_H__ */

drivers/gpu/drm/i915/display/intel_color.c

+31 −22
Original line number Diff line number Diff line
@@ -616,19 +616,19 @@ static void vlv_load_wgc_csc(struct intel_crtc *crtc, 
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pipe = crtc->pipe;



	intel_de_write_fw(dev_priv, PIPE_WGC_C01_C00(pipe),

	intel_de_write_fw(dev_priv, PIPE_WGC_C01_C00(dev_priv, pipe),

			  csc->coeff[1] << 16 | csc->coeff[0]);

	intel_de_write_fw(dev_priv, PIPE_WGC_C02(pipe),

	intel_de_write_fw(dev_priv, PIPE_WGC_C02(dev_priv, pipe),

			  csc->coeff[2]);



	intel_de_write_fw(dev_priv, PIPE_WGC_C11_C10(pipe),

	intel_de_write_fw(dev_priv, PIPE_WGC_C11_C10(dev_priv, pipe),

			  csc->coeff[4] << 16 | csc->coeff[3]);

	intel_de_write_fw(dev_priv, PIPE_WGC_C12(pipe),

	intel_de_write_fw(dev_priv, PIPE_WGC_C12(dev_priv, pipe),

			  csc->coeff[5]);



	intel_de_write_fw(dev_priv, PIPE_WGC_C21_C20(pipe),

	intel_de_write_fw(dev_priv, PIPE_WGC_C21_C20(dev_priv, pipe),

			  csc->coeff[7] << 16 | csc->coeff[6]);

	intel_de_write_fw(dev_priv, PIPE_WGC_C22(pipe),

	intel_de_write_fw(dev_priv, PIPE_WGC_C22(dev_priv, pipe),

			  csc->coeff[8]);

}
@@ -639,25 +639,25 @@ static void vlv_read_wgc_csc(struct intel_crtc *crtc, 
	enum pipe pipe = crtc->pipe;

	u32 tmp;



	tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C01_C00(pipe));

	tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C01_C00(dev_priv, pipe));

	csc->coeff[0] = tmp & 0xffff;

	csc->coeff[1] = tmp >> 16;



	tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C02(pipe));

	tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C02(dev_priv, pipe));

	csc->coeff[2] = tmp & 0xffff;



	tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C11_C10(pipe));

	tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C11_C10(dev_priv, pipe));

	csc->coeff[3] = tmp & 0xffff;

	csc->coeff[4] = tmp >> 16;



	tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C12(pipe));

	tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C12(dev_priv, pipe));

	csc->coeff[5] = tmp & 0xffff;



	tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C21_C20(pipe));

	tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C21_C20(dev_priv, pipe));

	csc->coeff[6] = tmp & 0xffff;

	csc->coeff[7] = tmp >> 16;



	tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C22(pipe));

	tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C22(dev_priv, pipe));

	csc->coeff[8] = tmp & 0xffff;

}
@@ -1227,7 +1227,7 @@ static void i9xx_load_lut_8(struct intel_crtc *crtc, 
	lut = blob->data;



	for (i = 0; i < 256; i++)

		intel_de_write_fw(dev_priv, PALETTE(pipe, i),

		intel_de_write_fw(dev_priv, PALETTE(dev_priv, pipe, i),

				  i9xx_lut_8(&lut[i]));

}
@@ -1240,9 +1240,11 @@ static void i9xx_load_lut_10(struct intel_crtc *crtc, 
	enum pipe pipe = crtc->pipe;



	for (i = 0; i < lut_size - 1; i++) {

		intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 0),

		intel_de_write_fw(dev_priv,

				  PALETTE(dev_priv, pipe, 2 * i + 0),

				  i9xx_lut_10_ldw(&lut[i]));

		intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 1),

		intel_de_write_fw(dev_priv,

				  PALETTE(dev_priv, pipe, 2 * i + 1),

				  i9xx_lut_10_udw(&lut[i]));

	}

}
@@ -1274,9 +1276,11 @@ static void i965_load_lut_10p6(struct intel_crtc *crtc, 
	enum pipe pipe = crtc->pipe;



	for (i = 0; i < lut_size - 1; i++) {

		intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 0),

		intel_de_write_fw(dev_priv,

				  PALETTE(dev_priv, pipe, 2 * i + 0),

				  i965_lut_10p6_ldw(&lut[i]));

		intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 1),

		intel_de_write_fw(dev_priv,

				  PALETTE(dev_priv, pipe, 2 * i + 1),

				  i965_lut_10p6_udw(&lut[i]));

	}
@@ -3150,7 +3154,8 @@ static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc) 
	lut = blob->data;



	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {

		u32 val = intel_de_read_fw(dev_priv, PALETTE(pipe, i));

		u32 val = intel_de_read_fw(dev_priv,

					   PALETTE(dev_priv, pipe, i));



		i9xx_lut_8_pack(&lut[i], val);

	}
@@ -3176,8 +3181,10 @@ static struct drm_property_blob *i9xx_read_lut_10(struct intel_crtc *crtc) 
	lut = blob->data;



	for (i = 0; i < lut_size - 1; i++) {

		ldw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 0));

		udw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 1));

		ldw = intel_de_read_fw(dev_priv,

				       PALETTE(dev_priv, pipe, 2 * i + 0));

		udw = intel_de_read_fw(dev_priv,

				       PALETTE(dev_priv, pipe, 2 * i + 1));



		i9xx_lut_10_pack(&lut[i], ldw, udw);

	}
@@ -3224,8 +3231,10 @@ static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc) 
	lut = blob->data;



	for (i = 0; i < lut_size - 1; i++) {

		u32 ldw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 0));

		u32 udw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 1));

		u32 ldw = intel_de_read_fw(dev_priv,

					   PALETTE(dev_priv, pipe, 2 * i + 0));

		u32 udw = intel_de_read_fw(dev_priv,

					   PALETTE(dev_priv, pipe, 2 * i + 1));



		i965_lut_10p6_pack(&lut[i], ldw, udw);

	}

drivers/gpu/drm/i915/display/intel_color_regs.h

+35 −7
Original line number Diff line number Diff line
@@ -8,7 +8,35 @@ 


#include "intel_display_reg_defs.h"



/* legacy palette */

/* GMCH palette */

#define _PALETTE_A		0xa000

#define _PALETTE_B		0xa800

#define _CHV_PALETTE_C		0xc000

/* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */

#define   PALETTE_RED_MASK		REG_GENMASK(23, 16)

#define   PALETTE_GREEN_MASK		REG_GENMASK(15, 8)

#define   PALETTE_BLUE_MASK		REG_GENMASK(7, 0)

/* pre-i965 10bit interpolated mode ldw */

#define   PALETTE_10BIT_RED_LDW_MASK	REG_GENMASK(23, 16)

#define   PALETTE_10BIT_GREEN_LDW_MASK	REG_GENMASK(15, 8)

#define   PALETTE_10BIT_BLUE_LDW_MASK	REG_GENMASK(7, 0)

/* pre-i965 10bit interpolated mode udw */

#define   PALETTE_10BIT_RED_EXP_MASK	REG_GENMASK(23, 22)

#define   PALETTE_10BIT_RED_MANT_MASK	REG_GENMASK(21, 18)

#define   PALETTE_10BIT_RED_UDW_MASK	REG_GENMASK(17, 16)

#define   PALETTE_10BIT_GREEN_EXP_MASK	REG_GENMASK(15, 14)

#define   PALETTE_10BIT_GREEN_MANT_MASK	REG_GENMASK(13, 10)

#define   PALETTE_10BIT_GREEN_UDW_MASK	REG_GENMASK(9, 8)

#define   PALETTE_10BIT_BLUE_EXP_MASK	REG_GENMASK(7, 6)

#define   PALETTE_10BIT_BLUE_MANT_MASK	REG_GENMASK(5, 2)

#define   PALETTE_10BIT_BLUE_UDW_MASK	REG_GENMASK(1, 0)

#define PALETTE(dev_priv, pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) +			\

			       _PICK_EVEN_2RANGES(pipe, 2,			\

						  _PALETTE_A, _PALETTE_B,	\

						  _CHV_PALETTE_C, _CHV_PALETTE_C) + \

						  (i) * 4)



/* ilk+ palette */

#define _LGC_PALETTE_A           0x4a000

#define _LGC_PALETTE_B           0x4a800

/* see PALETTE_* for the bits */
@@ -228,12 +256,12 @@ 
#define _PIPE_A_WGC_C21_C20	0x600C0 /* s2.10 */

#define _PIPE_A_WGC_C22		0x600C4 /* s2.10 */



#define PIPE_WGC_C01_C00(pipe)		_MMIO_TRANS2(pipe, _PIPE_A_WGC_C01_C00)

#define PIPE_WGC_C02(pipe)		_MMIO_TRANS2(pipe, _PIPE_A_WGC_C02)

#define PIPE_WGC_C11_C10(pipe)		_MMIO_TRANS2(pipe, _PIPE_A_WGC_C11_C10)

#define PIPE_WGC_C12(pipe)		_MMIO_TRANS2(pipe, _PIPE_A_WGC_C12)

#define PIPE_WGC_C21_C20(pipe)		_MMIO_TRANS2(pipe, _PIPE_A_WGC_C21_C20)

#define PIPE_WGC_C22(pipe)		_MMIO_TRANS2(pipe, _PIPE_A_WGC_C22)

#define PIPE_WGC_C01_C00(dev_priv, pipe)		_MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C01_C00)

#define PIPE_WGC_C02(dev_priv, pipe)		_MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C02)

#define PIPE_WGC_C11_C10(dev_priv, pipe)		_MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C11_C10)

#define PIPE_WGC_C12(dev_priv, pipe)		_MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C12)

#define PIPE_WGC_C21_C20(dev_priv, pipe)		_MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C21_C20)

#define PIPE_WGC_C22(dev_priv, pipe)		_MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C22)



/* pipe CSC & degamma/gamma LUTs on CHV */

#define _CGM_PIPE_A_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x67900)

drivers/gpu/drm/i915/display/intel_display.c

+1 −1
Original line number Diff line number Diff line
@@ -85,7 +85,6 @@ 
#include "intel_dvo.h"

#include "intel_fb.h"

#include "intel_fbc.h"

#include "intel_fbdev.h"

#include "intel_fdi.h"

#include "intel_fifo_underrun.h"

#include "intel_frontbuffer.h"
@@ -120,6 +119,7 @@ 
#include "skl_scaler.h"

#include "skl_universal_plane.h"

#include "skl_watermark.h"

#include "vlv_dpio_phy_regs.h"

#include "vlv_dsi.h"

#include "vlv_dsi_pll.h"

#include "vlv_dsi_regs.h"