Commit 9f94f545 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai
Browse files

clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent 



The only clock in the MT8183 MFGCFG block feeds the GPU. Propagate its
rate change requests to its parent, so that DVFS for the GPU can work
properly.

Fixes: acddfc2c ("clk: mediatek: Add MT8183 clock support")
Signed-off-by: default avatarChen-Yu Tsai <wenst@chromium.org>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220927101128.44758-3-angelogioacchino.delregno@collabora.com


Signed-off-by: default avatarChen-Yu Tsai <wenst@chromium.org>
parent 9ec105db

drivers/clk/mediatek/clk-mt8183-mfgcfg.c

+3 −3
Original line number Diff line number Diff line
@@ -19,8 +19,8 @@ static const struct mtk_gate_regs mfg_cg_regs = { 
};



#define GATE_MFG(_id, _name, _parent, _shift)				\

	GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift,	\

		&mtk_clk_gate_ops_setclr)

	GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift,	\

		       &mtk_clk_gate_ops_setclr, CLK_SET_RATE_PARENT)



static const struct mtk_gate mfg_clks[] = {

	GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0)