Commit 9f950e7d authored by Alvin Šipraga's avatar Alvin Šipraga Committed by Stephen Boyd
Browse files

dt-bindings: clock: si5351: add PLL reset mode property 



For applications where the PLL must be adjusted without glitches in the
clock output(s), a new silabs,pll-reset-mode property is added. It
can be used to specify whether or not the PLL should be reset after
adjustment. Resetting is known to cause glitches.

For compatibility with older device trees, it must be assumed that the
default PLL reset mode is to unconditionally reset after adjustment.

Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Jacob Siverskog <jacob@teenage.engineering>
Cc: Sergej Sawazki <sergej@taudac.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarAlvin Šipraga <alsi@bang-olufsen.dk>
Link: https://lore.kernel.org/r/20231124-alvin-clk-si5351-no-pll-reset-v6-2-69b82311cb90@bang-olufsen.dk


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 524dfbc4

Documentation/devicetree/bindings/clock/silabs,si5351.yaml

+24 −0
Original line number Diff line number Diff line
@@ -62,6 +62,27 @@ properties: 
        - description: PLL source, XTAL (0) or CLKIN (1, Si5351C only).

          enum: [ 0, 1 ]



  silabs,pll-reset-mode:

    $ref: /schemas/types.yaml#/definitions/uint32-matrix

    minItems: 1

    maxItems: 2

    description: A list of cell pairs containing a PLL index and its reset mode.

    items:

      items:

        - description: PLL A (0) or PLL B (1)

          enum: [ 0, 1 ]

        - description: |

            Reset mode for the PLL. Mode can be one of:



                0 - reset whenever PLL rate is adjusted (default mode)

                1 - do not reset when PLL rate is adjusted



            In mode 1, the PLL is only reset if the silabs,pll-reset is

            specified in one of the clock output child nodes that also sources

            the PLL. This mode may be preferable if output clocks are expected

            to be adjusted without glitches.

          enum: [ 0, 1 ]



patternProperties:

  "^clkout@[0-7]$":

    type: object
@@ -195,6 +216,9 @@ examples: 
        /* Use XTAL input as source of PLL0 and PLL1 */

        silabs,pll-source = <0 0>, <1 0>;



        /* Don't reset PLL1 on rate adjustment */

        silabs,pll-reset-mode = <1 1>;



        /*

         * Overwrite CLK0 configuration with:

         * - 8 mA output drive strength