Commit 9fa8cc0c authored by Michael Strauss's avatar Michael Strauss Committed by Alex Deucher
Browse files

drm/amd/display: Convert Delaying Aux-I Disable To Monitor Patch 



[WHY]
32ms delay was added to resolve issue with a specific sink, however this same
delay also introduces erroneous link training failures with certain sink
devices.

[HOW]
Only apply the 32ms delay for offending devices instead of globally.

Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarMichael Strauss <michael.strauss@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 550e5d23

drivers/gpu/drm/amd/display/dc/dc.h

+0 −1
Original line number Diff line number Diff line
@@ -855,7 +855,6 @@ struct dc_debug_options { 
	bool force_usr_allow;

	/* uses value at boot and disables switch */

	bool disable_dtb_ref_clk_switch;

	uint32_t fixed_vs_aux_delay_config_wa;

	bool extended_blank_optimization;

	union aux_wake_wa_options aux_wake_wa;

	uint32_t mst_start_top_delay;

drivers/gpu/drm/amd/display/dc/dc_types.h

+1 −0
Original line number Diff line number Diff line
@@ -196,6 +196,7 @@ struct dc_panel_patch { 
	unsigned int disable_fams;

	unsigned int skip_avmute;

	unsigned int mst_start_top_delay;

	unsigned int delay_disable_aux_intercept_ms;

};



struct dc_edid_caps {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

+11 −6
Original line number Diff line number Diff line
@@ -233,7 +233,8 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence_legacy( 
			link->dpcd_caps.lttpr_caps.phy_repeater_cnt);

	const uint8_t vendor_lttpr_write_data_intercept_en[4] = {0x1, 0x55, 0x63, 0x0};

	const uint8_t vendor_lttpr_write_data_intercept_dis[4] = {0x1, 0x55, 0x63, 0x68};

	uint32_t pre_disable_intercept_delay_ms = link->dc->debug.fixed_vs_aux_delay_config_wa;

	uint32_t pre_disable_intercept_delay_ms =

			link->local_sink->edid_caps.panel_patch.delay_disable_aux_intercept_ms;

	uint8_t vendor_lttpr_write_data_vs[4] = {0x1, 0x51, 0x63, 0x0};

	uint8_t vendor_lttpr_write_data_pe[4] = {0x1, 0x52, 0x63, 0x0};

	uint32_t vendor_lttpr_write_address = 0xF004F;
@@ -259,7 +260,7 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence_legacy( 


		/* Certain display and cable configuration require extra delay */

		if (offset > 2)

			pre_disable_intercept_delay_ms = link->dc->debug.fixed_vs_aux_delay_config_wa * 2;

			pre_disable_intercept_delay_ms = pre_disable_intercept_delay_ms * 2;

	}



	/* Vendor specific: Reset lane settings */
@@ -380,6 +381,7 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence_legacy( 
						0);

				/* Vendor specific: Disable intercept */

				for (i = 0; i < max_vendor_dpcd_retries; i++) {

					if (pre_disable_intercept_delay_ms != 0)

						msleep(pre_disable_intercept_delay_ms);

					dpcd_status = core_link_write_dpcd(

							link,
@@ -591,9 +593,11 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence( 
	const uint8_t vendor_lttpr_write_data_adicora_eq1[4] = {0x1, 0x55, 0x63, 0x2E};

	const uint8_t vendor_lttpr_write_data_adicora_eq2[4] = {0x1, 0x55, 0x63, 0x01};

	const uint8_t vendor_lttpr_write_data_adicora_eq3[4] = {0x1, 0x55, 0x63, 0x68};

	uint32_t pre_disable_intercept_delay_ms = link->dc->debug.fixed_vs_aux_delay_config_wa;

	uint8_t vendor_lttpr_write_data_vs[4] = {0x1, 0x51, 0x63, 0x0};

	uint8_t vendor_lttpr_write_data_pe[4] = {0x1, 0x52, 0x63, 0x0};

	uint32_t pre_disable_intercept_delay_ms =

			link->local_sink->edid_caps.panel_patch.delay_disable_aux_intercept_ms;





	uint32_t vendor_lttpr_write_address = 0xF004F;

	enum link_training_result status = LINK_TRAINING_SUCCESS;
@@ -618,7 +622,7 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence( 


		/* Certain display and cable configuration require extra delay */

		if (offset > 2)

			pre_disable_intercept_delay_ms = link->dc->debug.fixed_vs_aux_delay_config_wa * 2;

			pre_disable_intercept_delay_ms = pre_disable_intercept_delay_ms * 2;

	}



	/* Vendor specific: Reset lane settings */
@@ -739,6 +743,7 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence( 
						0);

				/* Vendor specific: Disable intercept */

				for (i = 0; i < max_vendor_dpcd_retries; i++) {

					if (pre_disable_intercept_delay_ms != 0)

						msleep(pre_disable_intercept_delay_ms);

					dpcd_status = core_link_write_dpcd(

							link,