Commit 9fae8245 authored by Andy Yan's avatar Andy Yan Committed by Heiko Stuebner
Browse files

drm/rockchip: vop2: Add delay between poll registers 



According to the implementation of read_poll_timeout_atomic, if the
delay time is 0, it will only use a simple loop based on timeout_us to
decrement the count. Therefore, the final timeout time will differ
significantly from the set timeout time. So, here we set a specific
delay time to ensure that the calculation of the timeout duration
is accurate.

Fixes: 3e89a8c6 ("drm/rockchip: vop2: Fix the update of LAYER/PORT select registers when there are multi display output on rk3588/rk3568")
Signed-off-by: default avatarAndy Yan <andy.yan@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Link: https://patch.msgid.link/20250718064120.8811-1-andyshrk@163.com
parent 3ea3b789

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

+2 −2
Original line number Diff line number Diff line
@@ -2104,7 +2104,7 @@ static void rk3568_vop2_wait_for_port_mux_done(struct vop2 *vop2) 
	 * Spin until the previous port_mux figuration is done.

	 */

	ret = readx_poll_timeout_atomic(rk3568_vop2_read_port_mux, vop2, port_mux_sel,

					port_mux_sel == vop2->old_port_sel, 0, 50 * 1000);

					port_mux_sel == vop2->old_port_sel, 10, 50 * 1000);

	if (ret)

		DRM_DEV_ERROR(vop2->dev, "wait port_mux done timeout: 0x%x--0x%x\n",

			      port_mux_sel, vop2->old_port_sel);
@@ -2124,7 +2124,7 @@ static void rk3568_vop2_wait_for_layer_cfg_done(struct vop2 *vop2, u32 cfg) 
	 * Spin until the previous layer configuration is done.

	 */

	ret = readx_poll_timeout_atomic(rk3568_vop2_read_layer_cfg, vop2, atv_layer_cfg,

					atv_layer_cfg == cfg, 0, 50 * 1000);

					atv_layer_cfg == cfg, 10, 50 * 1000);

	if (ret)

		DRM_DEV_ERROR(vop2->dev, "wait layer cfg done timeout: 0x%x--0x%x\n",

			      atv_layer_cfg, cfg);