Unverified Commit 9fe53abf authored by Alexander Usyskin's avatar Alexander Usyskin Committed by Rodrigo Vivi
Browse files

mtd: intel-dg: implement access functions 



Implement read(), erase() and write() functions.

CC: Lucas De Marchi <lucas.demarchi@intel.com>
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarRaag Jadav <raag.jadav@intel.com>
Acked-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Co-developed-by: default avatarTomas Winkler <tomasw@gmail.com>
Signed-off-by: default avatarTomas Winkler <tomasw@gmail.com>
Co-developed-by: default avatarVitaly Lubart <lubvital@gmail.com>
Signed-off-by: default avatarVitaly Lubart <lubvital@gmail.com>
Signed-off-by: default avatarAlexander Usyskin <alexander.usyskin@intel.com>
Link: https://lore.kernel.org/r/20250617145159.3803852-4-alexander.usyskin@intel.com


Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 7234b321

drivers/mtd/devices/mtd_intel_dg.c

+197 −0
Original line number Diff line number Diff line
@@ -5,13 +5,16 @@ 


#include <linux/bitfield.h>

#include <linux/bits.h>

#include <linux/delay.h>

#include <linux/device.h>

#include <linux/intel_dg_nvm_aux.h>

#include <linux/io.h>

#include <linux/io-64-nonatomic-lo-hi.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/string.h>

#include <linux/slab.h>

#include <linux/sizes.h>

#include <linux/types.h>



struct intel_dg_nvm {
@@ -91,6 +94,33 @@ static inline u32 idg_nvm_read32(struct intel_dg_nvm *nvm, u32 address) 
	return ioread32(base + NVM_TRIGGER_REG);

}



static inline u64 idg_nvm_read64(struct intel_dg_nvm *nvm, u32 address)

{

	void __iomem *base = nvm->base;



	iowrite32(address, base + NVM_ADDRESS_REG);



	return readq(base + NVM_TRIGGER_REG);

}



static void idg_nvm_write32(struct intel_dg_nvm *nvm, u32 address, u32 data)

{

	void __iomem *base = nvm->base;



	iowrite32(address, base + NVM_ADDRESS_REG);



	iowrite32(data, base + NVM_TRIGGER_REG);

}



static void idg_nvm_write64(struct intel_dg_nvm *nvm, u32 address, u64 data)

{

	void __iomem *base = nvm->base;



	iowrite32(address, base + NVM_ADDRESS_REG);



	writeq(data, base + NVM_TRIGGER_REG);

}



static int idg_nvm_get_access_map(struct intel_dg_nvm *nvm, u32 *access_map)

{

	u32 fmstr4_addr;
@@ -155,6 +185,173 @@ static int idg_nvm_is_valid(struct intel_dg_nvm *nvm) 
	return 0;

}



__maybe_unused

static unsigned int idg_nvm_get_region(const struct intel_dg_nvm *nvm, loff_t from)

{

	unsigned int i;



	for (i = 0; i < nvm->nregions; i++) {

		if ((nvm->regions[i].offset + nvm->regions[i].size - 1) >= from &&

		    nvm->regions[i].offset <= from &&

		    nvm->regions[i].size != 0)

			break;

	}



	return i;

}



static ssize_t idg_nvm_rewrite_partial(struct intel_dg_nvm *nvm, loff_t to,

				       loff_t offset, size_t len, const u32 *newdata)

{

	u32 data = idg_nvm_read32(nvm, to);



	if (idg_nvm_error(nvm))

		return -EIO;



	memcpy((u8 *)&data + offset, newdata, len);



	idg_nvm_write32(nvm, to, data);

	if (idg_nvm_error(nvm))

		return -EIO;



	return len;

}



__maybe_unused

static ssize_t idg_write(struct intel_dg_nvm *nvm, u8 region,

			 loff_t to, size_t len, const unsigned char *buf)

{

	size_t len_s = len;

	size_t to_shift;

	size_t len8;

	size_t len4;

	ssize_t ret;

	size_t to4;

	size_t i;



	idg_nvm_set_region_id(nvm, region);



	to4 = ALIGN_DOWN(to, sizeof(u32));

	to_shift = min(sizeof(u32) - ((size_t)to - to4), len);

	if (to - to4) {

		ret = idg_nvm_rewrite_partial(nvm, to4, to - to4, to_shift, (u32 *)&buf[0]);

		if (ret < 0)

			return ret;



		buf += to_shift;

		to += to_shift;

		len_s -= to_shift;

	}



	len8 = ALIGN_DOWN(len_s, sizeof(u64));

	for (i = 0; i < len8; i += sizeof(u64)) {

		u64 data;



		memcpy(&data, &buf[i], sizeof(u64));

		idg_nvm_write64(nvm, to + i, data);

		if (idg_nvm_error(nvm))

			return -EIO;

	}



	len4 = len_s - len8;

	if (len4 >= sizeof(u32)) {

		u32 data;



		memcpy(&data, &buf[i], sizeof(u32));

		idg_nvm_write32(nvm, to + i, data);

		if (idg_nvm_error(nvm))

			return -EIO;

		i += sizeof(u32);

		len4 -= sizeof(u32);

	}



	if (len4 > 0) {

		ret = idg_nvm_rewrite_partial(nvm, to + i, 0, len4, (u32 *)&buf[i]);

		if (ret < 0)

			return ret;

	}



	return len;

}



__maybe_unused

static ssize_t idg_read(struct intel_dg_nvm *nvm, u8 region,

			loff_t from, size_t len, unsigned char *buf)

{

	size_t len_s = len;

	size_t from_shift;

	size_t from4;

	size_t len8;

	size_t len4;

	size_t i;



	idg_nvm_set_region_id(nvm, region);



	from4 = ALIGN_DOWN(from, sizeof(u32));

	from_shift = min(sizeof(u32) - ((size_t)from - from4), len);



	if (from - from4) {

		u32 data = idg_nvm_read32(nvm, from4);



		if (idg_nvm_error(nvm))

			return -EIO;

		memcpy(&buf[0], (u8 *)&data + (from - from4), from_shift);

		len_s -= from_shift;

		buf += from_shift;

		from += from_shift;

	}



	len8 = ALIGN_DOWN(len_s, sizeof(u64));

	for (i = 0; i < len8; i += sizeof(u64)) {

		u64 data = idg_nvm_read64(nvm, from + i);



		if (idg_nvm_error(nvm))

			return -EIO;



		memcpy(&buf[i], &data, sizeof(data));

	}



	len4 = len_s - len8;

	if (len4 >= sizeof(u32)) {

		u32 data = idg_nvm_read32(nvm, from + i);



		if (idg_nvm_error(nvm))

			return -EIO;

		memcpy(&buf[i], &data, sizeof(data));

		i += sizeof(u32);

		len4 -= sizeof(u32);

	}



	if (len4 > 0) {

		u32 data = idg_nvm_read32(nvm, from + i);



		if (idg_nvm_error(nvm))

			return -EIO;

		memcpy(&buf[i], &data, len4);

	}



	return len;

}



__maybe_unused

static ssize_t

idg_erase(struct intel_dg_nvm *nvm, u8 region, loff_t from, u64 len, u64 *fail_addr)

{

	void __iomem *base = nvm->base;

	const u32 block = 0x10;

	u64 i;



	for (i = 0; i < len; i += SZ_4K) {

		iowrite32(from + i, base + NVM_ADDRESS_REG);

		iowrite32(region << 24 | block, base + NVM_ERASE_REG);

		/* Since the writes are via sgunit

		 * we cannot do back to back erases.

		 */

		msleep(50);

	}

	return len;

}



static int intel_dg_nvm_init(struct intel_dg_nvm *nvm, struct device *device)

{

	u32 access_map = 0;