Commit 9fe6690b authored by Benjamin Lin's avatar Benjamin Lin Committed by Felix Fietkau
Browse files

wifi: mt76: mt7996: add DMA support for mt7992 



Add DMA TX/RX queues and RRO init flow for mt7992 chipsets.
This is a preliminary patch for mt7992 chipsets support.

Co-developed-by: default avatarStanleyYP Wang <StanleyYP.Wang@mediatek.com>
Signed-off-by: default avatarStanleyYP Wang <StanleyYP.Wang@mediatek.com>
Co-developed-by: default avatarShayne Chen <shayne.chen@mediatek.com>
Signed-off-by: default avatarShayne Chen <shayne.chen@mediatek.com>
Signed-off-by: default avatarBenjamin Lin <benjamin-jw.lin@mediatek.com>
Signed-off-by: default avatarFelix Fietkau <nbd@nbd.name>
parent a63b75aa

drivers/net/wireless/mediatek/mt76/mt7996/dma.c

+47 −11
Original line number Diff line number Diff line
@@ -57,13 +57,19 @@ static void mt7996_dma_config(struct mt7996_dev *dev) 
	RXQ_CONFIG(MT_RXQ_MCU, WFDMA0, MT_INT_RX_DONE_WM, MT7996_RXQ_MCU_WM);

	RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_RX_DONE_WA, MT7996_RXQ_MCU_WA);



	/* band0/band1 */

	/* mt7996: band0 and band1, mt7992: band0 */

	RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0, MT7996_RXQ_BAND0);

	RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA0, MT_INT_RX_DONE_WA_MAIN, MT7996_RXQ_MCU_WA_MAIN);



	/* band2 */

	if (is_mt7996(&dev->mt76)) {

		/* mt7996 band2 */

		RXQ_CONFIG(MT_RXQ_BAND2, WFDMA0, MT_INT_RX_DONE_BAND2, MT7996_RXQ_BAND2);

		RXQ_CONFIG(MT_RXQ_BAND2_WA, WFDMA0, MT_INT_RX_DONE_WA_TRI, MT7996_RXQ_MCU_WA_TRI);

	} else {

		/* mt7992 band1 */

		RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_RX_DONE_BAND1, MT7996_RXQ_BAND1);

		RXQ_CONFIG(MT_RXQ_BAND1_WA, WFDMA0, MT_INT_RX_DONE_WA_EXT, MT7996_RXQ_MCU_WA_EXT);

	}



	if (dev->has_rro) {

		/* band0 */
@@ -90,8 +96,12 @@ static void mt7996_dma_config(struct mt7996_dev *dev) 


	/* data tx queue */

	TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7996_TXQ_BAND0);

	if (is_mt7996(&dev->mt76)) {

		TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7996_TXQ_BAND1);

		TXQ_CONFIG(2, WFDMA0, MT_INT_TX_DONE_BAND2, MT7996_TXQ_BAND2);

	} else {

		TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7996_TXQ_BAND1);

	}



	/* mcu tx queue */

	MCUQ_CONFIG(MT_MCUQ_WM, WFDMA0, MT_INT_TX_DONE_MCU_WM, MT7996_TXQ_MCU_WM);
@@ -111,6 +121,7 @@ static u32 __mt7996_dma_prefetch_base(u16 *base, u8 depth) 
static void __mt7996_dma_prefetch(struct mt7996_dev *dev, u32 ofs)

{

	u16 base = 0;

	u8 queue;



#define PREFETCH(_depth)	(__mt7996_dma_prefetch_base(&base, (_depth)))

	/* prefetch SRAM wrapping boundary for tx/rx ring. */
@@ -123,9 +134,14 @@ static void __mt7996_dma_prefetch(struct mt7996_dev *dev, u32 ofs) 
	mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU) + ofs, PREFETCH(0x2));

	mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU_WA) + ofs, PREFETCH(0x2));

	mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN_WA) + ofs, PREFETCH(0x2));

	mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2_WA) + ofs, PREFETCH(0x2));



	queue = is_mt7996(&dev->mt76) ? MT_RXQ_BAND2_WA : MT_RXQ_BAND1_WA;

	mt76_wr(dev, MT_RXQ_BAND1_CTRL(queue) + ofs, PREFETCH(0x2));



	mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN) + ofs, PREFETCH(0x10));

	mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2) + ofs, PREFETCH(0x10));



	queue = is_mt7996(&dev->mt76) ? MT_RXQ_BAND2 : MT_RXQ_BAND1;

	mt76_wr(dev, MT_RXQ_BAND1_CTRL(queue) + ofs, PREFETCH(0x10));



	if (dev->has_rro) {

		mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_RRO_BAND0) + ofs,
@@ -488,7 +504,7 @@ int mt7996_dma_init(struct mt7996_dev *dev) 
	if (ret)

		return ret;



	/* rx data queue for band0 and band1 */

	/* rx data queue for band0 and mt7996 band1 */

	if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) {

		dev->mt76.q_rx[MT_RXQ_MAIN].flags = MT_WED_Q_RX(0);

		dev->mt76.q_rx[MT_RXQ_MAIN].wed = wed;
@@ -517,7 +533,7 @@ int mt7996_dma_init(struct mt7996_dev *dev) 
		return ret;



	if (mt7996_band_valid(dev, MT_BAND2)) {

		/* rx data queue for band2 */

		/* rx data queue for mt7996 band2 */

		rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND2) + hif1_ofs;

		ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND2],

				       MT_RXQ_ID(MT_RXQ_BAND2),
@@ -527,7 +543,7 @@ int mt7996_dma_init(struct mt7996_dev *dev) 
		if (ret)

			return ret;



		/* tx free notify event from WA for band2

		/* tx free notify event from WA for mt7996 band2

		 * use pcie0's rx ring3, but, redirect pcie0 rx ring3 interrupt to pcie1

		 */

		if (mtk_wed_device_active(wed_hif2) && !dev->has_rro) {
@@ -542,6 +558,26 @@ int mt7996_dma_init(struct mt7996_dev *dev) 
				       MT_RXQ_RING_BASE(MT_RXQ_BAND2_WA));

		if (ret)

			return ret;

	} else if (mt7996_band_valid(dev, MT_BAND1)) {

		/* rx data queue for mt7992 band1 */

		rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND1) + hif1_ofs;

		ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1],

				       MT_RXQ_ID(MT_RXQ_BAND1),

				       MT7996_RX_RING_SIZE,

				       MT_RX_BUF_SIZE,

				       rx_base);

		if (ret)

			return ret;



		/* tx free notify event from WA for mt7992 band1 */

		rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND1_WA) + hif1_ofs;

		ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1_WA],

				       MT_RXQ_ID(MT_RXQ_BAND1_WA),

				       MT7996_RX_MCU_RING_SIZE,

				       MT_RX_BUF_SIZE,

				       rx_base);

		if (ret)

			return ret;

	}



	if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed) &&

drivers/net/wireless/mediatek/mt76/mt7996/init.c

+7 −2
Original line number Diff line number Diff line
@@ -513,7 +513,12 @@ void mt7996_mac_init(struct mt7996_dev *dev) 
	mt76_rmw_field(dev, MT_DMA_TCRF1(2), MT_DMA_TCRF1_QIDX, 0);



	/* rro module init */

	if (is_mt7996(&dev->mt76))

		mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 2);

	else

		mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE,

				   dev->hif2 ? 7 : 0);



	if (dev->has_rro) {

		u16 timeout;
@@ -570,7 +575,7 @@ static int mt7996_register_phy(struct mt7996_dev *dev, struct mt7996_phy *phy, 
	if (phy)

		return 0;



	if (band == MT_BAND2 && dev->hif2) {

	if (is_mt7996(&dev->mt76) && band == MT_BAND2 && dev->hif2) {

		hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);

		wed = &dev->mt76.mmio.wed_hif2;

	}

drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h

+5 −2
Original line number Diff line number Diff line
@@ -104,10 +104,10 @@ enum mt7996_rxq_id { 
	MT7996_RXQ_MCU_WM = 0,

	MT7996_RXQ_MCU_WA,

	MT7996_RXQ_MCU_WA_MAIN = 2,

	MT7996_RXQ_MCU_WA_EXT = 2,/* unused */

	MT7996_RXQ_MCU_WA_EXT = 3, /* for mt7992 */

	MT7996_RXQ_MCU_WA_TRI = 3,

	MT7996_RXQ_BAND0 = 4,

	MT7996_RXQ_BAND1 = 4,/* unused */

	MT7996_RXQ_BAND1 = 5, /* for mt7992 */

	MT7996_RXQ_BAND2 = 5,

	MT7996_RXQ_RRO_BAND0 = 8,

	MT7996_RXQ_RRO_BAND1 = 8,/* unused */
@@ -399,6 +399,9 @@ mt7996_phy3(struct mt7996_dev *dev) 
static inline bool

mt7996_band_valid(struct mt7996_dev *dev, u8 band)

{

	if (is_mt7992(&dev->mt76))

		return band <= MT_BAND1;



	/* tri-band support */

	if (band <= MT_BAND2 &&

	    mt76_get_field(dev, MT_PAD_GPIO, MT_PAD_GPIO_ADIE_COMB) <= 1)

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

+2 −2
Original line number Diff line number Diff line
@@ -461,12 +461,12 @@ enum base_rev { 
#define MT_INT1_MASK_CSR			MT_WFDMA0_PCIE1(0x204)



#define MT_INT_RX_DONE_BAND0			BIT(12)

#define MT_INT_RX_DONE_BAND1			BIT(12)

#define MT_INT_RX_DONE_BAND1			BIT(13) /* for mt7992 */

#define MT_INT_RX_DONE_BAND2			BIT(13)

#define MT_INT_RX_DONE_WM			BIT(0)

#define MT_INT_RX_DONE_WA			BIT(1)

#define MT_INT_RX_DONE_WA_MAIN			BIT(2)

#define MT_INT_RX_DONE_WA_EXT			BIT(2)

#define MT_INT_RX_DONE_WA_EXT			BIT(3) /* for mt7992 */

#define MT_INT_RX_DONE_WA_TRI			BIT(3)

#define MT_INT_RX_TXFREE_MAIN			BIT(17)

#define MT_INT_RX_TXFREE_TRI			BIT(15)