Commit 9fe9663e authored by Marc Zyngier's avatar Marc Zyngier Committed by Oliver Upton
Browse files

KVM: arm64: Expose GICv3 EL2 registers via KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 



Expose all the GICv3 EL2 registers through the usual GICv3 save/restore
interface, making it possible for a VMM to access the EL2 state.

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250714122634.3334816-7-maz@kernel.org


Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
parent 1d14c971

arch/arm64/kvm/vgic-sys-reg-v3.c

+113 −0
Original line number Diff line number Diff line
@@ -297,6 +297,91 @@ static int get_gic_sre(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, 
	return 0;

}



static int set_gic_ich_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,

			   u64 val)

{

	__vcpu_assign_sys_reg(vcpu, r->reg, val);

	return 0;

}



static int get_gic_ich_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,

			    u64 *val)

{

	*val = __vcpu_sys_reg(vcpu, r->reg);

	return 0;

}



static int set_gic_ich_apr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,

			   u64 val)

{

	u8 idx = r->Op2 & 3;



	if (idx > vgic_v3_max_apr_idx(vcpu))

		return -EINVAL;



	return set_gic_ich_reg(vcpu, r, val);

}



static int get_gic_ich_apr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,

			    u64 *val)

{

	u8 idx = r->Op2 & 3;



	if (idx > vgic_v3_max_apr_idx(vcpu))

		return -EINVAL;



	return get_gic_ich_reg(vcpu, r, val);

}



static int set_gic_icc_sre(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,

			   u64 val)

{

	if (val != KVM_ICC_SRE_EL2)

		return -EINVAL;

	return 0;

}



static int get_gic_icc_sre(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,

			   u64 *val)

{

	*val = KVM_ICC_SRE_EL2;

	return 0;

}



static int set_gic_ich_vtr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,

			   u64 val)

{

	if (val != kvm_get_guest_vtr_el2())

		return -EINVAL;

	return 0;

}



static int get_gic_ich_vtr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,

			   u64 *val)

{

	*val = kvm_get_guest_vtr_el2();

	return 0;

}



static unsigned int el2_visibility(const struct kvm_vcpu *vcpu,

				   const struct sys_reg_desc *rd)

{

	return vcpu_has_nv(vcpu) ? 0 : REG_HIDDEN;

}



#define __EL2_REG(r, acc, i)			\

	{					\

		SYS_DESC(SYS_ ## r),		\

		.get_user = get_gic_ ## acc,	\

		.set_user = set_gic_ ## acc,	\

		.reg = i,			\

		.visibility = el2_visibility,	\

	}



#define EL2_REG(r, acc)		__EL2_REG(r, acc, r)



#define EL2_REG_RO(r, acc)	__EL2_REG(r, acc, 0)



static const struct sys_reg_desc gic_v3_icc_reg_descs[] = {

	{ SYS_DESC(SYS_ICC_PMR_EL1),

	  .set_user = set_gic_pmr, .get_user = get_gic_pmr, },
@@ -328,6 +413,34 @@ static const struct sys_reg_desc gic_v3_icc_reg_descs[] = { 
	  .set_user = set_gic_grpen0, .get_user = get_gic_grpen0, },

	{ SYS_DESC(SYS_ICC_IGRPEN1_EL1),

	  .set_user = set_gic_grpen1, .get_user = get_gic_grpen1, },

	EL2_REG(ICH_AP0R0_EL2, ich_apr),

	EL2_REG(ICH_AP0R1_EL2, ich_apr),

	EL2_REG(ICH_AP0R2_EL2, ich_apr),

	EL2_REG(ICH_AP0R3_EL2, ich_apr),

	EL2_REG(ICH_AP1R0_EL2, ich_apr),

	EL2_REG(ICH_AP1R1_EL2, ich_apr),

	EL2_REG(ICH_AP1R2_EL2, ich_apr),

	EL2_REG(ICH_AP1R3_EL2, ich_apr),

	EL2_REG(ICH_HCR_EL2, ich_reg),

	EL2_REG_RO(ICC_SRE_EL2, icc_sre),

	EL2_REG_RO(ICH_VTR_EL2, ich_vtr),

	EL2_REG(ICH_VMCR_EL2, ich_reg),

	EL2_REG(ICH_LR0_EL2, ich_reg),

	EL2_REG(ICH_LR1_EL2, ich_reg),

	EL2_REG(ICH_LR2_EL2, ich_reg),

	EL2_REG(ICH_LR3_EL2, ich_reg),

	EL2_REG(ICH_LR4_EL2, ich_reg),

	EL2_REG(ICH_LR5_EL2, ich_reg),

	EL2_REG(ICH_LR6_EL2, ich_reg),

	EL2_REG(ICH_LR7_EL2, ich_reg),

	EL2_REG(ICH_LR8_EL2, ich_reg),

	EL2_REG(ICH_LR9_EL2, ich_reg),

	EL2_REG(ICH_LR10_EL2, ich_reg),

	EL2_REG(ICH_LR11_EL2, ich_reg),

	EL2_REG(ICH_LR12_EL2, ich_reg),

	EL2_REG(ICH_LR13_EL2, ich_reg),

	EL2_REG(ICH_LR14_EL2, ich_reg),

	EL2_REG(ICH_LR15_EL2, ich_reg),

};



static u64 attr_to_id(u64 attr)